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4286 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
REJ03B0251-0100 Rev.1.00 Aug 06, 2008
DESCRIPTION
The 4286 Group is a 4-bit single-chip microcomputer designed with CMOS technology for single-function remote control transmitters. The computer is equipped with an 8-bit timer (has two reload registers) can be set various carrier wave and an 8bit timer (has a reload register) can be control the carrier wave output automatically. The various microcomputers in the 4286 Group include variations of type as shown in the table below.
FEATURES
* Number of basic instructions ............................................. 72 * Minimum instruction execution time ............................ 2.0 s (at f(XIN) = 4.0 MHz, system clock = f(XIN)/2) * Supply voltage ................................................. 1.8 V to 3.6 V * Subroutine nesting ..................................................... 4 levels
* Timer Timer 1 ................................................................... 8-bit timer (This has a reload register and carrier wave output auto-control function) Timer 2 ................................................................... 8-bit timer (This has two reload registers and carrier wave output function) * Logic operation function (XOR, OR, AND) * RAM back-up function * Key-on wakeup function (ports D0-D7, E0-E2, G0-G3) .... 15 * I/O port (ports D, E, G, CARR) .......................................... 16 * Oscillation circuit ..................................... Ceramic resonance * Watchdog timer * Power-on reset circuit * Voltage drop detection circuit Before CLVD instruction execution Reset occurrence ............................... 1.5 V (Ta=25 C) Reset release .................................... 1.7 V (Ta=25 C) After CLVD instruction execution Reset occurrence/Reset release ........ 1.7 V (Ta=25 C)
APPLICATION
Consumer remote control transmitters
Part number M34286G2-XXXGP M34286G2GP
ROM size (x 9 bits) 2048 words 2048 words
RAM size (x 4 bits) 64 words 64 words
Package PLSP0020JB-A (20P2F-A) PLSP0020JB-A (20P2F-A)
ROM type QzROM QzROM (blank)
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4286 Group
PIN CONFIGURATION (TOP VIEW)
VSS E2 E1 XIN XOUT E0 G0 G1 G2 G3
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VDD CARR D0 D1 D2 D3 D4 D5 D6 D7
Outline: PLSP0020JB-A (20P2F-A)
M34286G2-XXXGP M34286G2GP
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4286 Group
1 2
4
1 8
BLOCK DIAGRAM
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Port E Port CARR Port D Port G System clock generation circuit XIN -XOUT Voltage drop detection circuit Power-on reset circuit
I/O port
Internal peripheral function
Timer/Remote-control carrier-wave output
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Timer 1 (8 bits, carrier wave output control)
Timer 2 (8 bits, carrier wave generation)
Watchdog timer (14 bits)
Memory
ROM
(2048 words 9 bits)
720 series CPU core
ALU(4 bits)
Register A (4 bits) Register B (4 bits) Register E (8 bits) Register D (3 bits) Stack register SK (4 levels)
RAM
(64 words 4 bits)
4286 Group
PERFORMANCE OVERVIEW
Parameter Number of basic instructions Memory sizes ROM RAM Input/Output ports D0-D7 I/O E0-E2 I/O G0-G3 I/O CARR Output Timer Timer 1 Timer 2 Subroutine nesting Device structure Package Operating temperature range Supply voltage Power Active mode dissipation (typical value) RAM back-up mode 72 2048 words 9 bits 64 words 4 bits Eight 1-bit I/O ports with the pull-down function and key-on wakeup function 3-bit I/O port with the pull-down function and key-on wakeup function 4-bit I/O port with the pull-down function and key-on wakeup function 1-bit output port; CMOS output 8-bit timer with a reload register 8-bit timer with two reload registers 4 levels (However, only 3 levels can be used when the TABP p instruction is executed) CMOS silicon gate 20-pin plastic molded LSSOP (PLSP0020JB-A (20P2F-A)) -40 to 85 C 1.8 V to 3.6 V 400 A (VDD = 3 V, STCK=f(XIN)/8, f(XIN) = 4 MHz) 0.1 A (Ta = 25 C, VDD = 3 V) Function
Minimum instruction execution time 2.0 s (f(XIN) = 4.0 MHz, system clock = f(XIN)/2, VDD = 3.0 V)
PIN DESCRIPTION
Pin VDD VSS XIN XOUT D0-D7 Name Power supply Ground System clock input System clock output I/O port D Input/Output -- -- Input Output I/O Connected to a plus power supply. Connected to a 0 V power supply. I/O pins of the system clock generating circuit. Connect a ceramic resonator between pins XIN and XOUT. The feedback resistor is built-in between pins XIN and XOUT. 1-bit I/O port. For input use, set the latch of the specified bit to "0." When the builtin pull-down transistor is turned on, the key-on wakeup function using "H" level sense and the pull-down transistor become valid. The output structure is P-channel open-drain. E0-E2 I/O port E Output Input 2-bit (E0, E1) output port. The output structure is P-channel open-drain. 3-bit input port. For input use (E0, E1), set the latch of the specified bit to "0." When the built-in pull-down transistor is turned on, the key-on wakeup function using "H" level sense and the pull-down transistor become valid. Port E2 has an input-only port and has a key-on wakeup function using "H" level sense and pulldown transistor. G0-G3 I/O port G I/O 4-bit I/O port. For input use, set the latch of the specified bit to "0." The output structure is P-channel open-drain. When the built-in pull-down transistor is turned on, the keyon wakeup function using "H" level sense and pull-down transistor become valid. CARR Carrier wave output for remote control Output Carrier wave output pin for remote control. The output structure is CMOS circuit. Function
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4286 Group
CONNECTIONS OF UNUSED PINS
Pin D0-D7 Connection Open (Set the output latch to "1" ). Open (Set the output latch to "0" ). Connect to VDD. E0, E1 Open (Set the output latch to "1" ). Open (Set the output latch to "0" ). Connect to VDD. E2 G0-G3 Open. Connect to VSS. Open (Set the output latch to "1" ). Open (Set the output latch to "0" ). Connect to VDD. CARR Open. Pull-down transistor OFF. Pull-down transistor OFF. Pull-down transistor OFF. Pull-down transistor OFF. Pull-down transistor OFF. Usage condition Pull-down transistor OFF.
(Note when connecting to VSS and VDD) * Connect the unused pins to VSS or VDD at the shortest distance and use the thick wire against noise.
PORT FUNCTION
Port Port D Pin D0-D7 Input/ Output I/O (8) Output structure P-channel open-drain Control bits 1 bit Control instructions SD RD CLD SZD Port E E0 E1 E2 Port G G0-G3 I/O (2) Input (1) I/O (4) Port CARR CARR Output CMOS (1) 1 bit P-channel open-drain 4 bits OGA IAG SCAR RCAR PU0 Pull-down function and key-on wakeup function (programmable) P-channel open-drain Output: OEA 2 bits Input: 3 bits IAE IAE PU0 Pull-down function and key-on wakeup function (programmable) Control registers PU1, PU2 Remark Pull-down function and key-on wakeup function (programmable)
DEFINITION OF CLOCK AND CYCLE
* System clock (STCK) The system clock is the source clock for controlling this product. It can be selected as shown below whether to use the Oscillation dividing instruction. CCK, CCK2, or CCK4 instruction can be executed only once. After one of their instruction is executed once, the operation is same as the NOP instruction though the same or another frequency dividing instruction is executed. The system clock returns to its initial state (f(XIN)/8) when system is returnd from RAM back-up mode.
Oscillation dividing instruction No use CCK used CCK2 used CCK4 used
* Instruction clock (INSTCK) The instruction clock is a signal derived by dividing the system clock by 4, and is the basic clock for controlling CPU. The one instruction clock cycle is equivalent to one machine cycle. * Machine cycle The machine cycle is the cycle required to execute the instruction.
System clock
f(XIN)/8 f(XIN) f(XIN)/2 f(XIN)/4
Instruction clock
f(XIN)/32 f(XIN)/4 f(XIN)/8 f(XIN)/16
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4286 Group
PORT BLOCK DIAGRAMS
Register Y SD instruction RD instruction CLD instruction Skip decision (SZD instruction) Key-on wakeup PU2i (Note 3) Register Y SD instruction RD instruction CLD instruction Skip decision (SZD instruction) Key-on wakeup (Note 2) PU1i Register A Aj (Note 3) Aj Key-on wakeup input (Note 3) PU0j IAE instruction Register A A2 Key-on wakeup input Pull-down transistor Pull-down transistor D OEA instruction T Q IAE instruction (Note 1) Pull-down transistor Decoder (Note 1) S R Q Decoder SQ R (Note 1)
Ports D0-D3 (Note 5)
(Note 1) Pull-down transistor
Ports D4-D7 (Note 5)
Ports E0, E1 (Note 5)
Port E2 (Note 5)
(Note 1)
Register A Aj (Note 3) Aj Key-on wakeup input PU02 Register A Ak (Note 4) Ak Key-on wakeup input Pull-down transistor PU03 CAR flag SCAR instruction RCAR instruction CARRYD (from timer 2) SQ R OGA instruction D T Q IAG instruction (Note 1) Pull-down transistor OGA instruction D T Q IAG instruction (Note 1)
Ports G0, G1 (Note 5)
Ports G2, G3 (Note 5)
CARRY (to timer 1)
(Note 1)
Port CARR
Timer 1 underflow signal V12
DQ TR V10
Carrier wave output control signal
Notes 1: This symbol represents a parasitic diode. 2: i represents bits 0 to 3. 3: j represents bits 0, 1. 4: k represents bits 2, 3. 5: Applied voltage must be less than VDD.
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4286 Group
FUNCTION BLOCK OPERATIONS CPU
(CY)
(1) Arithmetic logic unit (ALU) The arithmetic logic unit ALU performs 4-bit arithmetic such as 4-bit data addition, comparison, and bit manipulation. (2) Register A and carry flag Register A is a 4-bit register used for arithmetic, transfer, exchange, and I/O operation. Carry flag CY is a 1-bit flag that is set to "1" when there is a carry with the AMC instruction (Figure 1). It is unchanged with both A n instruction and AM instruction. The value of A0 is stored in carry flag CY with the RAR instruction (Figure 2). Carry flag CY can be set to "1" with the SC instruction and cleared to "0" with the RC instruction. (3) Registers B and E Register B is a 4-bit register used for temporary storage of 4bit data, and for 8-bit data transfer together with register A. Register E is an 8-bit register. It can be used for 8-bit data transfer with register B used as the high-order 4 bits and register A as the low-order 4 bits (Figure 3). (4) Register D Register D is a 3-bit register. It is used to store a 7-bit ROM address together with register A and is used as a pointer within the specified page when the TABP p, BLA p, or BMLA p instruction is executed (Figure 4).

(M(DP)) Addition (A)
Fig. 1 AMC instruction execution example
ALU
SC instruction
RC instruction
CY
A3 A2 A1 A0 RAR instruction
A0
CY A3 A2 A1
Fig. 2 RAR instruction execution example
Register B
TAB instruction
Register A
B3 B2 B1 B0
A3 A2 A1 A0
TEAB instruction Register E ER7ER6ER5ER4ER3ER2ER1ER0 TABE instruction B3 B2 B1 B0 Register B A3 A2 A1 A0 TBA instruction Register A
Fig. 3 Registers A, B and register E
TABP p instruction Specifying address 8
ROM 4 0 Low-order 4 bits
PCH p3 p2 p1 p0
PCL DR2 DR1 DR0 A3 A2 A1 A0
Register A (4) Middle-order 4 bits Register B (4) Most significant 1 bit Carry flag CY (1)
Immediate field value p
The contents of register D
The contents of register A
URS flag (1) URSC instruction
Fig. 4 TABP p instruction execution example
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4286 Group
(5) Most significant ROM code reference enable flag (URS) URS flag controls whether to refer to the contents of the most significant 1 bit (bit 8) of ROM code when executing the TABP p instruction. If URS flag is "0," the contents of the most significant 1 bit of ROM code is not referred even when executing the TABP p instruction. However, if URS flag is "1," the contents of the most significant 1 bit of ROM code is set to flag CY when executing the TABP p instruction (Figure 4). URS flag is "0" after system is released from reset and returned from RAM back-up mode. It can be set to "1" with the URSC instruction, but cannot be cleared to "0." (6) Stack registers (SKs) and stack pointer (SP) Stack registers (SKs) are used to temporarily store the contents of program counter (PC) just before branching until returning to the original routine when; * performing a subroutine call, or * executing the table reference instruction (TABP p). Stack registers (SKs) are four identical registers, so that subroutines can be nested up to 4 levels. However, one of stack registers is used when executing a table reference instruction. Accordingly, be careful not to over the stack. The contents of registers SKs are destroyed when 4 levels are exceeded. The register SK nesting level is pointed automatically by 2-bit stack pointer (SP). Figure 5 shows the stack registers (SKs) structure. Figure 6 shows the example of operation at subroutine call. (7) Skip flag Skip flag controls skip decision for the conditional skip instructions and continuous described skip instructions. Note : The 4286 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes "1" if the TABP p, RT, or RTS instruction is skipped.
Program counter (PC) Executing BM instruction SK0 SK1 SK2 SK3 Executing RT instruction (SP) = 0 (SP) = 1 (SP) = 2 (SP) = 3
Stack pointer (SP) points "3" at reset or returning from RAM back-up mode. It points "0" by executing the first BM instruction, and the contents of program counter is stored in SK0. When the BM instruction is executed after four stack registers are used ((SP) = 3), (SP) = 0 and the contents of SK0 is destroyed.
Fig. 5 Stack registers (SKs) structure
(SP) 0 (SK0) 000116 (PC) SUB1
Main program Address 000016 NOP 000116 BM SUB1 000216 NOP
Subroutine
SUB1 : NOP * * * RT
(PC) (SK0) (SP) 3
Note: Returning to the BM instruction execution address with the RT instruction, and the BM instruction is equivalent to the NOP instruction.
Fig. 6 Example of operation at subroutine call
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4286 Group
(8) Program counter (PC) Program counter (PC) is used to specify a ROM address (page and address). It determines a sequence in which instructions stored in ROM are read. It is a binary counter that increments the number of instruction bytes each time an instruction is executed. However, the value changes to a specified address when branch instructions, subroutine call instructions, return instructions, or the table reference instruction (TABP p) is executed. Program counter consists of PCH (most significant bit to bit 7) which specifies to a ROM page and PCL (bits 6 to 0) which specifies an address within a page. After it reaches the last address (address 127) of a page, it specifies address 0 of the next page (Figure 7). Make sure that the PCH does not exceed after the last page of the built-in ROM. (9) Data pointer (DP) Data pointer (DP) is used to specify a RAM address and consists of registers X and Y. Register X specifies a file and register Y specifies a RAM digit (Figure 8). Register Y is also used to specify the port D bit position. When using port D, set the port D bit position to register Y certainly and execute the SD, RD, or SZD instruction (Figure 9).
Program counter (PC) p3 p2 p1 p0 a6 a5 a4 a3 a2 a1 a0
PCH Specifying page
PCL Specifying address
Fig. 7 Program counter (PC) structure
Data pointer (DP) X1 X0 Y3 Y2 Y1 Y0
Register Y (4)
Specifying RAM digit
Register X (2)
Specifying RAM file
Fig. 8 Data pointer (DP) structure
Specifying bit position Set
D7 D5 D0
0
101
Register Y (4)
1 Port D output latch
Fig. 9 SD instruction execution example
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4286 Group
PROGRAM MEMORY (ROM)
The program memory is a mask ROM. 1 word of ROM is composed of 9 bits. ROM is separated every 128 words by the unit of page (addresses 0 to 127). Table 1 ROM size and pages Part number M34286G2 ROM size ( 9 bits) 2048 words Pages 16 (0 to 15)
8 000016 007F16 008016 00FF16 010016 017F16 018016 7 6 5 4 3 2 10 Page 0 Page 1 Subroutine special page Page 2 Page 3
Page 2 (addresses 010016 to 017F16) is the special page for subroutine calls. Subroutines written in this page can be called from any page with the 1-word instruction (BM). Subroutines extending from page 2 to another page can also be called with the BM instruction when it starts on page 2. ROM pattern of all addresses can be used as data areas with the TABP p instruction.
07FF16
Page 15
Fig. 10 ROM map of M34286G2
DATA MEMORY (RAM)
1 word of RAM is composed of 4 bits, but 1-bit manipulation (with the SB j, RB j, and SZB j instructions) is enabled for the entire memory area. A RAM address is specified by a data pointer. The data pointer consists of registers X and Y. Set a value to the data pointer certainly when executing an instruction to access RAM. Table 2 shows the RAM size. Figure 11 shows the RAM map. Table 2 RAM size Part number M34286G2
RAM 64 words 4 bits (256 bits)
Register X
01
2
3
RAM size 64 words 4 bits (256 bits)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 64 words M34286G2
Fig. 11 RAM map
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Register Y
4286 Group
TIMERS
The 4286 Group has the programmable timer. * Programmable timer The programmable timer has a reload register and enables the frequency dividing ratio to be set. It is decremented from a setting value n. When it underflows (count to n + 1), a timer 1 underflow flag is set to "1," new data is loaded from the reload register, and count continues (auto-reload function).
FF16 n: Counter initial value Count starts n The contents of counter 1st underflow 2nd underflow Reload Reload
0016 Time n+1 count Timer 1 underflow flag "1" "0" A skip instruction is executed n+1 count
Fig. 12 Auto-reload function The 4286 Group timer consists of the following circuit. * Timer 1 : 8-bit programmable timer * Timer 2 : 8-bit programmable timer These timers can be controlled with the timer control registers V1 and V2. Each timer function is described below. Table 3 Function related timer Circuit Timer 1 Timer 2 14-bit timer Structure 8-bit programmable binary down counter 8-bit programmable binary down counter Count source Frequency dividing ratio Use of output signal * Carrier wave output control * Carrier wave output * Watchdog timer * Timer 1 count source Control register V1 V2
* Carrier wave output (CARRY) 1 to 256 * Bit 5 of watchdog timer * f(XIN) * f(XIN)/2 16384 1 to 256
14-bit fixed frequency * Instruction clock
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4286 Group
V10 (Note 1) V11
0 1
SNZT1 instruction Timer 1 (8)
CARRY
0 1
T1F
Timer 1 underflow signal (to port CARR)
Reload register R1 (8)
(T1AB)(Note 2)
(TAB1)
Register B Register A
(TAB1)
Register B
Register A
(T2HAB)
Reload register R2H (8) V20 (Note 1)
0 1
V23 Timer 2(8)
Reload control circuit T R Q SNZT2 instruction T2F T2F
(TAB2) CARRYD (to port CARR)
V21
XIN
1/2
0 1
(Note 3) (T2R2L)
(T2AB)
V22
(T2AB)
Reload register R2L (8)
(TAB2)
Register B
Register A
CAR flag SCAR instruction RCAR instruction SQ R
CARRY (to timer 1) Port CARR
Timer 1 underflow signal
DQ TR
Carrier wave output control signal
V12
V10
Initializing signal (Note 4) System reset 13 WDF1 WDF2
14-bit timer (WDT) INSTCK 0 5
WRST instruction Initializing signal (Note 4)
Notes 1: Counting is stopped by clearing to "0." 2: When the T1AB instruction is executed after V10 is set to "1," writing is performed only to reload register R1. 3: The data of reload register R2L set with the T2AB instruction can be also written to timer 2 with the T2R2L instruction. 4: The initializing signal is output at reset or RAM back-up mode.
Fig. 13 Timers structure
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4286 Group
Table 4 Control registers related to timer Timer control register V1 V12 V11 V10 Carrier wave output auto-control bit Timer 1 count source selection bit Timer 1 control bit 0 1 0 1 0 1 at reset : 0002 at RAM back-up : 0002 W
Auto-control output by timer 1 is invalid Auto-control output by timer 1 is valid Carrier wave output (CARRY) Bit 5 of watchdog timer (WDT) Stop (Timer 1 state retained) Operating at reset : 00002 at RAM back-up : 00002 W
Timer control register V2 V23 V22 V21 V20 Carrier wave "H" interval expansion bit Carrier wave generation function control bit Timer 2 count source selection bit Timer 2 control bit 0 1 0 1 0 1 0 1
To expand "H" interval is invalid To expand "H" interval is valid (when V22=1 selected) Carrier wave generation function invalid Carrier wave generation function valid f(XIN) f(XIN)/2 Stop (Timer 2 state retained) Operating
Note: "W" represents write enabled. (1) Control registers related to timer * Timer control register V1 Register V1 controls the timer 1 count source and autocontrol function of carrier wave output from port CARR by timer 1. Set the contents of this register through register A with the TV1A instruction. * Timer control register V2 Register V2 controls the timer 2 count source and the carrier wave generation function by timer. Set the contents of this register through register A with the TV2A instruction. (2) Precautions Note the following for the use of timers. * Count source Stop timer 1 or timer 2 counting to change its count source. * Reading the count value Stop timer 1 or 2 counting and then execute the data read instruction (TAB1, TAB2) to read its data. * Watchdog timer Be sure that the timing to execute the WRST instruction in order to operate WDT efficiently. * Writing to reload register R1 When writing data to reload register R1 while timer 1 is operating, avoid a timing when timer 1 underflows. * Timer 1 count operation When the bit 5 of the watchdog timer (WDT) is selected as the timer 1 count source, the error of maximum 64 s (at the minimum instruction execution time : 2 s) is generated from timer 1 start until timer 1 underflow. When programming, be careful about this error. * Stop of timer 2 Avoid a timing when timer 2 underflows to stop timer 2. * Writing to reload register R2H When writing data to reload register R2H while timer 2 is operating, avoid a timing when timer underflows. * Timer 2 carrier wave output function When to expand "H" interval of carrier wave is valid, set "1" or more to reload register R2H. * Timer 1 and timer 2 carrier wave output function Count starts from the rising edge in Fig. 14 after the first falling edge of the count source, after timer 1 and timer 2 operations start in Fig. 14. Time to first underflow in Fig. 14 is different from time among next underflow in Fig. 14 by the timing to start the timer and count source operations after count starts.
Count source Timer value 3 2 1 0 3 2 1 0 3
Timer underflow signal
Timer start
Fig. 14 Count start time and count time when operation starts (T1, T2)
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4286 Group
(3) Timer 1 Timer 1 is an 8-bit binary down counter with the timer 1 reload register (R1). When timer is stopped, data can be set simultaneously in timer 1 and the reload register (R1) with the T1AB instruction. When timer is operating, data can be set to only reload register R1 with the T1AB instruction. When setting the next count data to reload register R1 at operating, set data before timer 1 underflows. Timer 1 starts counting after the following process; set data in timer 1, select the count source with the bit 1 of register V1, and set the bit 0 of register V1 to "1." Once count is started, when timer 1 underflows (the next count pulse is input after the contents of timer 1 becomes "0"), the timer 1 underflow flag (T1F) is set to "1," new data is loaded from reload register R1, and count continues (auto-reload function). When a value set in reload register R1 is n, timer 1 divides the count source signal by n + 1 (n = 0 to 255). When the bit 2 of register V1 is set to "1," the carrier wave output enable/disable interval of port CARR is alternately generated each timer 1 underflows (Figure 15). Data can be read from timer 1 to registers A and B. When reading the data, stop the counter and then execute the TAB1 instruction. (4) Timer 2 Timer 2 is an 8-bit binary down counter with the timer 2 reload registers (R2H and R2L). Data can be set simultaneously in timer 2 and the reload register (R2L) with the T2AB instruction. The contents of reload register (R2L) set with the T2AB instruction can be set again to timer 2 with the T2R2L instruction. Data can be set to reload register (R2H) with the T2HAB instruction. Timer 2 starts counting after the following process; set data in timer 2, select the count source with the bit 1 of register V2, and select the valid/invalid of the carrier wave generation function by bit 2 of register V1 (when this function is valid, select the valid/invalid of the carrier wave "H" interval expansion by bit 3), and set the bit 0 of register V1 to "1." When the carrier wave generation function is invalid (V22="0"), the following operation is performed; Once count is started, when timer 2 underflows (the next count pulse is input after the contents of timer 2 becomes "0"), the timer 2 underflow flag (T2F) is set to "1," new data is loaded from reload register R2L, and count continues (auto-reload function). When a value set in reload register R2L is n, timer 2 divides the count source signal by n + 1 (n = 0 to 255). When the carrier wave generation function is valid (V22="1"), the carrier wave which has the "L" interval set to the reload register R2L and "H" interval set to the reload register R2H can be output (Figure 16). After the count of the "L" interval of carrier wave is started, timer 2 underflows and the timer 2 underflow flag (T2F) is set
to "1". Then, the "H" interval data of carrier wave is reloaded from the reload register R2H, and count continues. When timer underflows again after auto-reload, the T2F flag is set to "1". And then, the "L" interval data of carrier wave is reloaded from the reload register R2L, and count continues. After that, each timer underflows, data is reloaded from reload register R2H and R2L alternately. When a value set in reload register R2H is n, "H" interval of carrier wave is as follows; When to expand "H" interval is invalid (V23 = "0"), Count source (n+1), n = 0 to 255 When to expand "H" interval is valid (V23 = "1"), Count source (n+1.5), n = 1 to 255 When a value set in reload register R2L is m, "L" interval of carrier wave is as follows; Count source (m+1), m = 0 to 255 Data can be read from timer 2 to registers A and B. When reading the data, stop the counter and then execute the TAB2 instruction. (5) Timer underflow flags (T1F, T2F) Timer 1 underflow flag or timer 2 underflow flag is set to "1" when the timer 1 or timer 2 underflows. The state of flags T1F and T2F can be examined with the skip instruction (SNZT1, SNZT2). Flags T1F and T2F are cleared to "0" when the next instruction is skipped with a skip instruction.
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4286 Group
Timer 1 starts
Timer 1 underflow
"1" "0" "H"
(V10)1
Port CARR output "L"
Set the interval "a" to timer 1. Set the interval "b" Set the interval "c" to reload register R1. to reload register R1. Count source CARRY selected
(V11)0
a
b
Set the interval "d" to reload register R1.
c
d
Auto-control valid
(V12)1
Carrier wave output start
Timer 1 stop
(V10)0
Timer 1 underflow
"1" "0" "H"
CARRY "L" Port CARR output
(Note)
"H" "L" "0"
Register V12 "1"
Carrier wave output start Auto-control invalid Auto-control invalid Carrier wave output stop
Note: When timer 1 is stopped, the port CARR output auto-control is terminated regardless of bit 2 (V12) of register V1.
Fig. 15 Port CARR output control by timer 1
In this case, the following is set; * Timer 2 carrier wave generation function is valid (V22="1"), * "L" interval (0316) of carrier wave is set to reload register R2L * "H" interval (0216) of carrier wave is set to reload register R2H
To expand "H" interval of carrier wave is invalid (V23="0") [Count source: 4.0 MHz, Resolution: 250 ns]
Timer 2 count source Timer 2 count value 0316 (Reload register) Timer 2 underflow signal CARRYD Timer 2 starts
3 clocks interval 3 clocks interval
0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 (R2H) (R2L) (R2H) (R2L) (R2H)
(R2L)
Carrier wave period: 7 clocks
Carrier wave period: 7 clocks
To expand "H" interval of carrier wave is valid (V23="1") (When count source is 4.0 MHz, carrier wave is expanded for 125 ns]
Timer 2 count source Timer 2 count value 0316 (Reload register) (R2L) (R2H) Timer 2 underflow signal CARRYD Timer 2 starts
3.5 clocks interval 3.5 clocks interval
0216 0116 0016
0216
0116 0016 0316 0216 0116 0016 (R2L)
0216 (R2H)
0116 0016 0316 0216 0116 0016 (R2L)
0216 (R2H)
Carrier wave period: 7.5 clocks
Carrier wave period: 7.5 clocks
Note: When to expand "H" interval of the carrier wave is valid, set "0116" or more to reload register R2H.
Fig. 16 Carrier wave generation example by timer 2
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4286 Group
In this case, the following is set; * To expand "H" interval of carrier wave is invalid (V23 = "0"), * Timer 2 carrier wave generation function is valid (V22="1"), * Count source XIN/2 selected (V21="1"), * "L" interval (0316) of carrier wave is set to reload register R2L * "H" interval (0216) of carrier wave is set to reload register R2H Timer 2 count start timing
Machine cycle Mi
Mi + 1
Mi + 2
TV2A instruction execution cycle (V20) 1
Instruction clock =f(XIN)/8 XIN XIN/2 (Count source selected) Register V20 Timer 2 count value (Reload register) Timer 2 underflow signal CARRYD 0316 (R2L) 0216 0116 0016 0216 0116 0016 0316 0216 (R2H) (R2L)
Timer 2 count start timing
Timer 2 count stop timing
Machine cycle Mi
Mi + 1 Mi + 2
TV2A instruction execution cycle (V20)0
Instruction clock =f(XIN)/8 XIN XIN/2 (Count source selected) Register V20 Timer 2 count value (Reload register) Timer 2 underflow signal (Note 1) 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 (R2L) (R2H) (R2L) 0216 (R2H)
CARRYD
Timer 2 count stop timing Notes 1: When the carrier wave generation function is valid (V22="1"), avoid a timing when timer 2 underflows to stop timer 2. When the timer 2 count stop occurs at the same timing with the timer 2 underflows, hazard may occur in the carrier wave output waveform. 2: When the timer 2 is stopped during "H" output of carrier wave while the carrier wave generation function is valid, it is stopped after the "H" interval set by reload register R2H is output.
Fig. 17 Timer 2 count start/stop timing
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4286 Group
WATCHDOG TIMER
Watchdog timer provides a method to reset and restart the system when a program runs wild. Watchdog timer consists of 14-bit timer (WDT) and watchdog timer flags (WDF1, WDF2). Watchdog timer downcounts the instruction clock (INSTCK) as the count source immediately after system is released from reset. When the timer WDT count value becomes 000016 and underflow occurs, the WDF1 flag is set to "1." Then, when the WRST instruction is not executed before the timer WDT counts 16383, WDF2 flag is set to "1" and internal reset signal is generated and system reset is performed. Execute the WRST instruction at period of 16383 machine cycle or less to keep the microcomputer operation normal. Timer WDT is also used for generation of oscillation stabilization time. When system is returned from reset and from RAM backup mode by key-input, software starts after the stabilization oscillation time until timer WDT downcounts to 3E0016 elapses.
* Watchdog timer Be sure that the timing to execute the WRST instruction in order to operate WDT efficiently.
Software start
Software start
Software start
3FFF16 3E0016
Value of timer WDT
0000 16
WDF1 flag WDF2 flag "1" "0" "1" "0" "H" "L" POF instruction execution Return
Internal reset signal
System reset
Fig. 18 Watchdog timer function
WRST instruction execution
System reset
LOGIC OPERATION FUNCTION
The 4286 Group has the 4-bit logic operation function. The logic operation between the contents of register A and the low-order 4 bits of register E is performed and its result is stored in register A.
Each logic operation can be selected by setting logic operation selection register LO. Set the contents of this register through register A with the TLOA instruction. The logic operation selected by register LO is executed with the LGOP instruction. Table 5 shows the logic operation selection register LO.
Table 5 Logic operation selection register LO Logic operation selection register LO LO1 Logic operation selection bits LO0 Note: "W" represents write enabled. LO1 0 0 1 1 at reset : 002 LO0 0 1 0 1 at RAM back-up : 002 W
Logic operation function Exclusive logic OR operation (XOR) OR operation (OR) AND operation (AND) Not available
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4286 Group
RESET FUNCTION
The 4286 Group has the power-on reset circuit, though it does not have RESET pin. System reset is performed automatically at power-on, and software starts program from address 0 in page 0. In order to make the built-in power-on reset circuit operate efficiently, set the voltage rising time until VDD= 0 to 2.2 V is obtained at power-on 1ms or less (Ta = -20 C to 85 C).
Note on Power-on reset Under the following condition, the system reset occurs by the built-in the power-on reset circuit of this product; - when the supply voltage (VDD) rises from 0 V to 2.2 V, within 1 ms (Ta = -20 C to 85 C). Also, note that system reset does not occur under the following conditions; - when the supply voltage (VDD) rises from the voltage higher than 0V, or - when it takes more than 1 ms for the supply voltage (VDD) to rise from 0 V to 2.2 V (Ta = -20 C to 85 C).
f(XIN)
Internal reset signal "H"
"L"
f(XIN) 16384 pulses
Software operation starts (address 0 in page 0)
Fig. 19 Reset release timing
VDD
Internal reset signal
Power-on reset circuit output voltage
Power-on reset circuit Reset state Voltage drop detection circuit Watchdog timer output Internal reset signal
Reset released Power-on
Fig. 20 Power-on reset operation (1) Internal state at reset Table 6 shows port state at reset, and Figure 21 shows internal state at reset (they are retained after system is released from reset). The contents of timers, registers, flags and RAM except shown in Figure 21 are undefined, so set the initial value to them. Table 6 Port state at reset State at reset Name D0-D7 G0-G3 E0, E1 CARR High impedance state (Pull-down transistor OFF) High impedance state (Pull-down transistor OFF) High impedance state (Pull-down transistor OFF) "L" output
Note: The contents of all output latch is initialized to "0."
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4286 Group
* Program counter (PC) .............................................................. Address 0 in page 0 is set to program counter. * Power down flag (P) ................................................................. * Timer 1 underflow flag (T1F) ................................................... * Timer 2 underflow flag (T2F) ................................................... * Timer control register V1 .......................................................... * Timer control register V2 .......................................................... * Port CARR output flag (CAR) .................................................. * Pull-down control register PU0 ................................................ * Pull-down control register PU1 ................................................ * Pull-down control register PU2 ................................................ * Logic operation selection register LO ...................................... * Most significant ROM code reference enable flag (URS) * Carry flag (CY) ......................................................................... * Register A ................................................................................. * Register B ................................................................................. * Register X ................................................................................. * Register Y ................................................................................. * Stack pointer (SP) .................................................................... Fig. 21 Internal state at reset
0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
0
0
0
0
0
0
0
0
0
0
0 0 0 0 0 0
0 0 0 0 0
0 0 0 0
111 111 1
"" represents undefined.
VOLTAGE DROP DETECTION CIRCUIT
System reset is performed when the supply voltage goes the reset occurrence voltage or less. When the supply voltage goes reset release voltage or more, the oscillation circuit goes to be in the operating enabled state and system reset is released. The reset occurrence voltage value is selectable by the CLVD instruction execution. Refer to the electrical characteristics for reset occurrence value and reset release voltage value. The voltage drop detection circuit is stopped and power dissipation is reduced in the RAM back-up mode with the initialized CPU stopped. Note on voltage drop detection circuit The voltage drop detection circuit detection voltage of this product is set up lower than the minimum value of the supply voltage of the recommended operating conditions. As the actual operating minimum voltage is lower than the reset generation voltage, the MCU will operate correctly unless oscillation stops before the supply voltage reaches the reset generation voltage during CPU operation. When designing a system, test the operation thoroughly by confirming the oscillation stop voltage and frequency of the oscillator.
VDD Recommended operating condition min.value VDET Oscillation is stopped incorrectly. Even if the voltage re-goes up to the recommended operating voltage, MCU may not operate correctly.
VDD Recommended operating condition min.value VDET
Normal operation
Reset
Fig. 23 VDD and VDET
VDD Reset occurrence/release voltage TYP = 1.7V Reset occurrence voltage TYP = 1.5V
Internal reset signal
(Note)
(Note)
CLVD instruction
Note: Microcomputer starts operation after f(XIN) is counted to 16384 times.
Fig. 22 Voltage drop detection circuit operation waveform
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4286 Group
RAM BACK-UP MODE
The 4286 Group has the RAM back-up mode. When the POF instruction is executed, system enters the RAM back-up state. As oscillation stops retaining RAM, the functions and states of reset circuit at RAM back-up mode, power dissipation can be reduced without losing the contents of RAM. Table 7 shows the function and states retained at RAM back-up. Figure 24 shows the state transition. (1) Warm start condition When the external wakeup signal is input after the system enters the RAM back-up state by executing the POF instruction, the CPU starts executing the software from address 0 in page 0. In this case, the P flag is "1." (2) Cold start condition The CPU starts executing the software from address 0 in page 0 when any of the following conditions is satisfied . * reset by power-on reset circuit is performed * reset by watchdog timer is performed * reset by voltage drop detection circuit is performed In this case, the P flag is "0." (3) Identification of the start condition Warm start (return from the RAM back-up state) or cold start (return from the normal reset state) can be identified by examining the state of the power down flag (P) with the SNZP instruction.
Table 7 Functions and states retained at RAM back-up Function Program counter (PC), registers A, B, carry flag (CY), stack pointer (SP) (Note 2) Contents of RAM Port CARR Ports D0-D7 Ports E0, E1 Port G Timer control registers V1, V2 Pull-down control registers PU0, PU1, PU2 Logic operation selection register LO Timer 1 function, Timer 2 function Timer underflow flags (T1F, T2F) Watchdog timer (WDT) Watchdog timer flags (WDF1, WDF2) Most significant ROM code reference enable flag (URS) RAM back-up O O O O O
Notes 1: "O" represents that the function can be retained, and "" represents that the function is initialized. Registers and flags other than the above are undefined at RAM back-up, and set an initial value after returning. 2:The stack pointer (SP) points the level of the stack register and is initialized to "112" at RAM back-up.
A (Stabilizing time a ) Reset f(XIN) oscillation
POF instruction is executed
B f(XIN) stop
Return input (Stabilizing time a )
(RAM back-up mode)
Stabilizing time a : Microcomputer starts its operation after f(XIN) is counted to16384 times.
Fig. 24 State transition
Power down flag P POF instruction Reset input S Q
Software start P = "1" ? No Cold start Yes
R
Set source Clear source
POF instruction is executed Reset input
Warm start
Fig. 25 Set source and clear source of the P flag
Fig. 26 Start condition identified example using the SNZP instruction
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4286 Group
(4) Return signal An external wakeup signal is used to return from the RAM back-up mode. Table 8 shows the return condition for each return source. Table 8 Return source and return condition Return source Ports D0-D7 Ports E0, E1, G Port E2 input. input. input. (5) Pull-down control register Registers PU0, PU1, and PU2 are 4-bit registers and control the ON/OFF of pull-down transistor and key-on wakeup function for ports E0, E1, G and ports D0-D7. Table 9 Pull-down control registers Pull-down control register PU0 PU03 PU02 PU01 PU00 Ports G2, G3 pull-down transistor control bit Ports G0, G1 pull-down transistor control bit Port E1 pull-down transistor control bit Port E0 pull-down transistor control bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained W Set the contents of register PU0, PU1, or PU2 through register A with the TPU0A, TPU1A, or TPU2A instruction, respectively. Return condition Remarks turned ON by register PU1 and PU2 are valid. turned ON by register PU0 is valid. Return by an external "H" level Only key-on wakeup function of the port whose pull-down transistor is Return by an external "H" level Only key-on wakeup function of the port whose pull-down transistor is Return by an external "H" level Key-on wakeup function is always valid.
Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid
Pull-down control register PU1 PU13 PU12 PU11 PU10 Port D7 pull-down transistor control bit Port D6 pull-down transistor control bit Port D5 pull-down transistor control bit Port D4 pull-down transistor control bit 0 1 0 1 0 1 0 1
at reset : 00002
at RAM back-up : state retained
W
Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid
Pull-down control register PU2 PU23 PU22 PU21 PU20 Port D3 pull-down transistor control bit Port D2 pull-down transistor control bit Port D1 pull-down transistor control bit Port D0 pull-down transistor control bit 0 1 0 1 0 1 0 1
at reset : 00002
at RAM back-up : state retained
W
Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid
Note: "W" represents write enabled.
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4286 Group
CLOCK CONTROL
The clock control circuit consists of the following circuits. * System clock generating circuit * Control circuit to stop the clock oscillation * Control circuit to return from the RAM back-up state
CCK/CCK2/CCK4 instruction XIN XOUT Frequency divider (divided by 8) Frequency divider (divided by 4) Frequency divider (divided by 2) Frequency divider
(through mode)
OSC
Frequency divider (divided by 4)
INSTCK Instruction clock
Multiplexer
STCK
Internal power-on reset circuit POF instruction R S Q Pull-down control register PU0 Pull-down control register PU1, PU2 Ports E0,E1,G0-G3
Ports D0-D7 Port E2
CCK, CCK2, or CCk4 instruction can be executed only once. After one of their instruction is executed once, the operation is same as the NOP instruction though the same or another frequency dividing instruction is executed.
Fig. 27 Clock control circuit structure System clock signal f(XIN) is obtained by externally connecting a ceramic resonator. Connect this external circuit to pins XIN and XOUT at the shortest distance as shown Figure 28. A feedback resistor is built-in between XIN pin and XOUT pin.
4286
XIN 4
XOUT 5
Use the resonator manufacturer's recommended value because constants such as capacitance depend on the resonator.
CIN
COUT
Fig. 28 Ceramic resonator external circuit
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4286 Group
LIST OF PRECAUTIONS
Noise and latch-up prevention Connect a capacitor on the following condition to prevent noise and latch-up; * connect a bypass capacitor (approx. 0.01 F) between pins VDD and VSS at the shortest distance, * equalize its wiring in width and length, and * use the thickest wire. * Port E2 is also used as VPP pin. Connect this pin to VSS through the resistor about 5k which is assigned to E2/VPP pin as close as possible at the shortest distance. Register initial values 1 The initial value of the following registers are undefined after system is released from reset. After system is released from reset, set initial values. * Register D (3 bits) * Register E (8 bits) Register initial values 2 The initial value of the following registers are undefined at RAM backup. After system is returned from RAM back-up, set initial values. * Register X (4 bits) * Register Y (4 bits) * Register D (3 bits) * Register E (8 bits) Stack registers (SKS) Stack registers (SKs) are four identical registers, so that subroutines can be nested up to 4 levels. However, one of stack registers is used when executing a table reference instruction. Accordingly, be careful not to over the stack. The contnts of registers SKs are destroyed when 4 levels are exceeded. Notes on unused pins
Timer * Count source Stop timer 1 or timer 2 counting to change its count source. * Reading the count value Stop timer 1 or 2 counting and then execute the data read instruction (TAB1, TAB2) to read its data. * Watchdog timer Be sure that the timing to execute the WRST instruction in order to operate WDT efficiently. * Writing to reload register R1 When writing data to reload register R1 while timer 1 is operating, avoid a timing when timer 1 underflows. * Timer 1 count operation When the bit 5 of the watchdog timer (WDT) is selected as the timer 1 count source, the error of maximum 64 s (at the minimum instruction execution time : 2 s) is generated from timer 1 start until timer 1 underflow. When programming, be careful about this error. * Stop of timer 2 Avoid a timing when timer 2 underflows to stop timer 2. * Writing to reload register R2H When writing data to reload register R2H while timer 2 is operating, avoid a timing when timer underflows. * Timer 2 carrier wave output function When to expand "H" interval of carrier wave is valid, set "1" or more to reload register R2H. * Timer 1 and timer 2 carrier wave output function Count starts from the rising edge in Fig. 29 after the first falling edge of the count source, after timer 1 and timer 2 operations start in Fig. 29. Time to first underflow in Fig. 29 is different from time among next underflow in Fig. 29 by the timing to start the timer and count source operations after count starts.
Count source
Pin
Connection Open (Set the output latch to "0" ). Connect to VDD. Open (Set the output latch to "0" ). Connect to VDD.
Usage condition
Timer value 3 2 1 0 3 2 1 0 3
D0-D7 Open (Set the output latch to "1" ). Pull-down transistor OFF. Pull-down transistor OFF.
Timer underflow signal
Timer start
Pull-down transistor OFF.
E2
Open. Connect to VSS.
Fig. 29 Count start time and count time when operation starts (T1, T2) Program counter Make sure that the program counter does not specify after the last page of the built-in ROM.
G0-G3 Open (Set the output latch to "1" ). Pull-down transistor OFF. Open (Set the output latch to "0" ). Connect to VDD. CARR Open. Pull-down transistor OFF.
(Note when connecting to VSS and VDD) * Connect the unused pins to VSS and VDD at the shortest distance and use the thick wire against noise.
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E0, E1 Open (Set the output latch to "1" ). Pull-down transistor OFF.
4286 Group
Power-on reset Under the following condition, the system reset occurs by the built-in the power-on reset circuit of this product; - when the supply voltage (VDD) rises from 0 V to 2.2 V, within 1 ms (Ta = -20 C to 85 C). Also, note that system reset does not occur under the following conditions; - when the supply voltage (VDD) rises from the voltage higher than 0V, or - when it takes more than 1 ms for the supply voltage (VDD) to rise from 0 V to 2.2 V (Ta = -20 C to 85 C). Voltage drop detection circuit The voltage drop detection circuit detection voltage of this product is set up lower than the minimum value of the supply voltage of the recommended operating conditions. As the actual operating minimum voltage is lower than the reset generation voltage, the MCU will operate correctly unless oscillation stops before the supply voltage reaches the reset generation voltage during CPU operation. When designing a system, test the operation thoroughly by confirming the oscillation stop voltage and frequency of the oscillator.
11
QzROM
(1) Be careful not to apply overvoltage to MCU. The contents of QzROM may be overwritten because of overvoltage. Take care especially at turning on the power. (2) As for the product shipped in blank, Renesas does not perform the writing test to user ROM area after the assembly process though the QzROM writing test is performed enough before the assembly process. Therefore, a writing error of approx.0.1 % may occur. Moreover, please note the contact of cables and foreign bodies on a socket, etc. because a writing environment may cause some writing errors.
12
Notes On ROM Code Protect (QzROM product shipped after writing) As for the QzROM product shipped after writing, the ROM code protect is specified according to the ROM option setup data in the mask file which is submitted at ordering. The ROM option setup data in the mask file is "0016" for protect enabled or "FF16" for protect disabled. Note that the mask file which has nothing at the ROM option data or has the data other than "0016" and "FF16" can not be accepted.
VDD Recommended operating condition min.value VDET Oscillation is stopped incorrectly. Even if the voltage re-goes up to the recommended operating voltage, MCU may not operate correctly.
VDD Recommended operating condition min.value VDET
Normal operation
Reset
Fig. 30 VDD and VDET Note on Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the supply voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation.
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4286 Group
INSTRUCTIONS
The 4286 Group has the 72 instructions. Each instruction is described as follows; (1) List of instruction function (2) Machine instructions (index by alphabet) (3) Machine instructions (index by function) (4) Instruction code table
SYMBOL
The symbols shown below are used in the following list of instruction function and the machine instructions. Symbol A B DR ER V1 V2 PU0 PU1 PU2 LO X Y DP PC PCH PCL SK SP CY R1 T1 T1F R2H R2L T2 T2F WDT WDF1 WDF2 URS P STCK INSTCK Register A (4 bits) Register B (4 bits) Register D (3 bits) Register E (8 bits) Timer control register V1 (3 bits) Timer control register V2 (4 bits) Pull-down control register PU0 (4 bits) Pull-down control register PU1 (4 bits) Pull-down control register PU2 (4 bits) Logic operation selection register LO (2 bits) Register X (2 bits) Register Y (4 bits) Data pointer (6 bits) (It consists of registers X and Y) Program counter (11 bits) High-order 4 bits of program counter Low-order 7 bits of program counter Stack register (11 bits 4) Stack pointer (2 bits) Carry flag Timer 1 reload register Timer 1 Timer 1 underflow flag Timer 2 reload register Timer 2 reload register Timer 2 Timer 2 underflow flag Watchdog timer Watchdog timer flag 1 Watchdog timer flag 2 Most significant ROM code reference enable flag Power down flag System clock Instruction clock C + x M(DP) a p, a ? () -- Direction of data movement Data exchange between a register and memory Decision of state shown before "?" Contents of registers and memories Negate, Flag unchanged after executing instruction RAM address pointed by the data pointer Label indicating address a6 a5 a4 a3 a2 a1 a0 Label indicating address a6 a5 a4 a3 a2 a1 a0 in page p3 p2 p1 p0 Hex. number C + Hex. number x (also same for others) A3A2A1A0 j p n Hexadecimal variable Hexadecimal constant which represents the immediate value Hexadecimal constant which represents the immediate value Binary notation of hexadecimal variable A (same for others) x y Hexadecimal variable Hexadecimal variable Contents D E G CARR CAR Symbol Port D (8 bits) Port E (3 bits) Port G (4 bits) Port CARR (1 bit) CAR flag (1 bit) Contents
Note : The 4286 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes "1" if the TABP p, RT, or RTS instruction is skipped.
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4286 Group
LIST OF INSTRUCTION FUNCTION
Grouping Mnemonic
Function (A) (B) (B) (A) (A) (Y) (Y) (A) (ER7-ER4) (B) (ER3-ER0) (A)
Page 41 43
Grouping Mnemonic
Function (A) n n = 0 to 15
Page 34
TAB TBA
LA n
TABP p
Register to register transfer
(SP) (SP) + 1 (SK(SP)) (PC) (PCH) p p=0 to 15 (PCL) (DR2-DR0, A3-A0) When URS=0 (B) (ROM(PC))7 to 4 (A) (ROM(PC))3 to 0 When URS=1
42
TAY TYA TEAB
43 45 43
TABE
(B) (ER7-ER4) (A) (ER3-ER0)
42
(CY) (ROM(PC))8 (B) (ROM(PC))7 to 4 (A) (ROM(PC))3 to 0
TDA LXY x, y
(DR2-DR0) (A2-A0) (X) x, x = 0 to 3 (Y) y, y = 0 to 15
43 34
(PC) (SK(SP)) (SP) (SP) - 1
RAM addresses
Arithmetic operation
AM AMC
(A) (A) + (M(DP)) (A) (A) + (M(DP)) + (CY) (CY) Carry
29 29
INY DEY TAM j
(Y) (Y) + 1 (Y) (Y) - 1 (A) (M(DP)) (X) (X) EXOR(j) j = 0 to 3
33 33 42
An
(A) (A) + n n = 0 to 15
29
SC 46 RC SZC 46 CMA RAR LGOP
(CY) 1 (CY) 0 (CY) = 0 ? (A) (A) CY A3A2A1A0 Logic operation instruction XOR, OR, AND
37 36 40 32 35 34
XAM j
(A) (M(DP)) (X) (X) EXOR(j) j = 0 to 3
XAMD j
(A) (M(DP)) (X) (X) EXOR(j) j = 0 to 3 (Y) (Y) - 1
RAM to register transfer
XAMI j
(A) (M(DP)) (X) (X) EXOR(j) j = 0 to 3 (Y) (Y) + 1
46
SB j
(Mj(DP)) 1 j = 0 to 3
37
Bit operation
RB j
(Mj(DP)) 0 j = 0 to 3
36
SZB j
(Mj(DP)) = 0 ? j = 0 to 3
39
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4286 Group
Grouping Mnemonic
Function (A) = (M(DP)) ? (A) = n ? n = 0 to 15
Page 38 38
Grouping Mnemonic
Function (V12-V10) (A2-A0) (B) (T17-T14) (A) (T13-T10)
Page 45 41
Comparison
SEAM
TV1A TAB1
operation
SEA n
Ba
(PCL) a6-a0 (PCH) p (PCL) a6-a0
29 30
T1AB
at timer 1 stop (V10=0): (R17-R14) (B) (T17-T14) (B) (R13-R10) (A) (T13-T10) (A)
40
Branch operation
BL p, a
BA a BLA p, a
(PCL) (a6-a4, A3-A0) (PCH) p (PCL) (a6-a4, A3-A0)
30 30 SNZT1
at timer 1 operating (V10=1): (R17-R14) (B) (R13-R10) (A) (T1F) = 1 ? (T1F) 0 TV2A TAB2 (V23-V20) (A3-A0) (B) (T27-T24) (A) (T23-T20) 45 42 39
BM a
(SP) (SP) + 1 (SK(SP)) (PC) (PCH) 2 (PCL) a6-a0
30
Subroutine operation
BML p, a (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p p= 0 to 15 (PCL) a6-a0 BMLA p, (SP) (SP) + 1 (SK(SP)) (PC) a (PCH) p p= 0 to 15 (PCL) (a6-a4, A3-A0)
31
Timer operation
T2AB
(R2L7-R2L4) (B) (T27-T24) (B) (R2L3-R2L0) (A) (T23-T20) (A)
40
31
T2HAB
(R2H7-R2H4) (B) (R2H3-R2H0) (A)
41
Return operation
RT
(PC) (SK(SP)) (SP) (SP) - 1
37
T2R2L
(T27-T24) (R2L7-R2L4) (T23-T20) (R2L3-R2L0)
41
RTS
(PC) (SK(SP)) (SP) (SP) - 1
37
SNZT2
(T2F) = 1 ? (T2F) 0
39
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4286 Group
LIST OF INSTRUCTION FUNCTION (CONTINUED)
Grouping Mnemonic
Function (D) 0 (D(Y)) 0 (Y) = 0 to 7
Page 32 36
CLD RD
SD
(D(Y)) 1 (Y) = 0 to 7
38
Input/Output operation
SZD
(D(Y)) = 0 ? (Y) = 0 to 7
40
OEA IAE OGA IAG
(E1, E0) (A1, A0) (A2-A0) (E2-E0) (G) (A) (A) (G) (CAR) 1 (CAR) 0
35 33 35 33 38 36
control operation
Carrier wave
SCAR RCAR
NOP POF SNZP CCK CCK2
(PC) (PC) + 1 RAM back-up (P) = 1 ? STCK changes to f(XIN) STCK changes to f(XIN)/2 STCK changes to f(XIN)/4 Reset occurrence voltage value changes (LO1, LO0) (A1, A0) (URS) 1 (PU03-PU00) (A3-A0) (PU13-PU10) (A3-A0) (PU23-PU20) (A3-A0) (WDF1) 0
34 35 39 31 31 32 32 44 45 44 44 44 46
Other operation
CCK4 CLVD TLOA URSC TPU0A TPU1A TPU2A WRST
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4286 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET)
A n (Add n and accumulator)
Instruction code D8 0 1 0 1 0 D0 n3 n2 n1 n0
2
0
A
n
Number of words
16
Number of cycles 1
Flag CY -
Skip condition Overflow = 0
1 Operation: (A) (A) + (M(DP))
n = 0 to 15
Grouping: Arithmetic operation Description: Adds the value n in the immediate field to register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation.
AM (Add accumulator and Memory)
Instruction code D8 0 0 0 0 0 1 0 1 D0 0
2
0
0
A
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1 Grouping:
Operation:
(A)
(A) + (M(DP))
Arithmetic operation
Description: Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged.
AMC (Add accumulator, Memory and Carry)
Instruction code D8 0 0 0 0 0 1 0 1 D0 1
2
0
0
B
Number of words
16
Number of cycles 1
Flag CY 0/1
Skip condition -
1 Grouping:
Operation:
(A) (A) + (M(DP)) + (CY) Carry (CY)
Arithmetic operation
Description: Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY.
B a (Branch to address a)
Instruction code D8 1 1 D0 a6 a5 a4 a3 a2 a1 a0
2
1
8 +a
a
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1 Grouping:
Operation:
(PCL)
a6-a0
Branch operation
Description: Branch within a page : Branches to address a in the identical page.
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4286 Group
BA a (Branch to address a + Accumulator)
Instruction code D8 0 1 Operation: 0 1 0 0 0 0 0 0 D0 1
2 2
0 1
0 8 +a
1 a
Number of words
16 16
Number of cycles 2
Flag CY -
Skip condition -
2 Grouping:
a6 a5 a4 a3 a2 a1 a0 a6-a4, A3-A0
Branch operation
(PCL)
Description: Branch within a page : Branches to address (a6 a5 a4 A3 A2 A1 A0) determined by replacing the low-order 4 bits of the address a in the identical page with register A.
BL p, a (Branch Long to address a in page p)
Instruction code D8 0 1 Operation: 0 1 0 1 1 D0 p3 p2 p1 p0
2
0 1
3 8 +a
p a
Number of words
16
Number of cycles 2
Flag CY -
Skip condition -
2 Grouping:
a6 a5 a4 a3 a2 a1 a0 (P) a6-a0
2
16
Branch operation
(PCH) (PCL)
Description: Branch out of a page : Branches to address a in page p. Note: p is 0 to 15.
BLA p, a (Branch Long to address a in page p)
Instruction code D8 0 1 Operation: 0 1 0 0 1 0 0 0 D0 0
2
0 1
1 8 +a
0 p
Number of words
16
Number of cycles 2
Flag CY -
Skip condition -
2 Grouping:
a6 a5 a4 p3 p2 p1 p0 (P) (a6-a4, A3-A0)
2
16
Branch operation
(PCH) (PCL)
Description: Branch within a page : Branches to address (a6 a5 a4 A3 A2 A1 A0) determined by replacing the low-order 4 bits of the address a in page p with register A. p is 0 to 15. Note:
BM a (Branch and Mark to address a in page 2)
Instruction code D8 1 0 D0 a6 a5 a4 a3 a2 a1 a0
2
1
a
a
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1 Grouping:
Operation:
(SK(SP)) (SP) (PCH) (PCL) 2
(PC)
Subroutine call operation
(SP) + 1 a6-a0
Description: Call the subroutine in page 2 : Calls the subroutine at address a in page 2.
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4286 Group
BML p, a
Instruction code
(Branch and Mark Long to address a in page p)
D8 0 1 0 0 1 1 1 D0 p3 p2 p1 p0
2 2
0 1
7 a
p a
Number of words
16
Number of cycles 2
Flag CY -
Skip condition -
2 a6 a5 a4 a3 a2 a1 a0
16
Grouping:
Subroutine call operation
Operation:
(SK(SP)) (PC) (SP) (SP) + 1 p (PCH) (PCL) a6-a0
Description: Call the subroutine : Calls the subroutine at address a in page p. Note: p is 0 to 15.
BMLA p, a (Branch and Mark Long to address a in page p)
Instruction code D8 0 1 Operation: 0 0 1 0 1 0 0 0 D0 0
2 2
0 1
5 a
0 p
Number of words
16 16
Number of cycles 2
Flag CY -
Skip condition -
2 Grouping:
a6 a5 a4 p3 p2 p1 p0
Subroutine call operation
(SK(SP)) (PC) (SP) (SP) + 1 (PCH) p (a6-a4, A3-A0) (PCL)
Description: Call the subroutine : Calls the subroutine at address (a6 a5 a4 A3 A2 A1 A0) determined by replacing the low-order 4 bits of address a in page p with register A. Note: p is 0 to 15.
CCK (Change system Clock to f(XIN))
Instruction code D8 0 0 1 0 1 1 0 0 D0 1
2
0
5
9
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1 Grouping:
Operation:
Change to STCK = f(XIN)
Other operation
Description: Changes system clock (STCK) from f(XIN)/8 to f(XIN).
CCK2 (Change system Clock to f(XIN)/2)
Instruction code D8 0 0 0 0 1 1 0 0 D0 1 0 1 9
16
Number of words 1 Grouping:
Number of cycles 1
Flag CY -
Skip condition -
Operation:
Change to STCK = f(XIN)/2
Other operation
Description: Changes system clock (STCK) from f(XIN)/8 to f(XIN)/2.
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4286 Group
CCK4 (Change system Clock to f(XIN)/4)
Instruction code D8 0 0 0 1 0 1 1 0 D0 1 0 2 D
16
Number of words 1 Grouping:
Number of cycles 1
Flag CY -
Skip condition -
Operation:
Change to STCK = f(XIN)/4
Other operation
Description: Changes system clock (STCK) from f(XIN)/8 to f(XIN)/4.
CLD (CLear port D)
Instruction code D8 0 0 0 0 1 0 0 0 D0 1
2
0
1
1
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1 Grouping:
Operation:
(D)
0
Input/Output operation
Description: Clears (0) to port D (high-impedance state).
CLVD (Change Voltage Drop Detection)
Instruction code D8 0 0 0 1 0 1 1 1 D0 0 0 2 E
16
Number of words 1 Grouping:
Number of cycles 1
Flag CY -
Skip condition -
Operation:
Reset occurrence voltage 1.5
1.7V
Other operation
Description: Change reset occurrence voltage from1.5V to 1.7V (Ta = 25C, Typ).
CMA (CoMplement of Accumulator)
Instruction code D8 0 0 0 0 1 1 1 0 D0 0
2
0
1
C
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1 Grouping:
Operation:
(A)
(A)
Arithmetic operation
Description: Stores the one's complement for register A's contents in register A.
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4286 Group
DEY (DEcrement register Y)
Instruction code D8 0 0 0 0 1 0 1 1 D0 1
2
0
1
7
Number of words
16
Number of cycles 1
Flag CY -
Skip condition (Y) = 15
1 Grouping:
Operation:
(Y)
(Y) - 1
RAM addresses
Description: Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped.
IAE (Input Accumulator from port E)
Instruction code D8 0 0 1 0 1 0 1 1 D0 0
2
0
5
6
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1 Grouping:
Operation:
(A2-A0)
(E2-E0)
Input/Output operation
Description: Transfers the contents of port E to register A.
IAG (Input Accumulator from port G)
Instruction code D8 0 0 0 1 0 1 0 0 D0 0
2
0
2
8
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1 Grouping:
Operation:
(A)
(G)
Input/Output operation
Description: Transfers the contents of port G to register A.
INY (INcrement register Y)
Instruction code D8 0 0 0 0 1 0 0 1 D0 1
2
0
1
3
Number of words
16
Number of cycles 1
Flag CY -
Skip condition (Y) = 0
1 Grouping:
Operation:
(Y)
(Y) + 1
RAM addresses
Description: Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped.
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4286 Group
LA n (Load n in Accumulator)
Instruction code D8 0 1 0 1 1 D0 n3 n2 n1 n0
2
0
B
n
Number of words
16
Number of cycles 1
Flag CY -
Skip condition Continuous description
1 Grouping:
Operation:
(A) n n = 0 to 15
Arithmetic operation
Description: Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously are skipped.
LGOP (LoGic OPeration between accumulator and register E)
Instruction code D8 0 0 1 0 0 0 0 0 D0 1
2
0
4
1
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1 Grouping:
Operation:
Logic operation XOR, OR, AND
Arithmetic operation
Description: Executes the logic operation selected by logic operation selection register LO between the contents of register A and register E, and stores the result in register A.
LXY x, y (Load register X and Y with x and y)
Instruction code D8 0 1 1 D0 x1 x0 y3 y2 y1 y0
2
0
C +x
y
Number of words
16
Number of cycles 1
Flag CY -
Skip condition Continuous description
1 Grouping:
Operation:
(X) (Y)
x, x = 0 to 3 y, y = 0 to 15
RAM addresses
Description: Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y. When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continuously are skipped.
NOP (No OPeration)
Instruction code D8 0 0 0 0 0 0 0 0 D0 0
2
0
0
0
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1 Grouping:
Operation:
(PC)
(PC) + 1
Other operation
Description: No operation
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4286 Group
OEA (Output port E from Accumulator)
Instruction code D8 0 1 0 0 0 0 1 0 D0 0
2
0
8
4
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1 Grouping:
Operation:
(E1, E0)
(A1, A0)
Input/Output operation
Description: Outputs the contents of register A to port E.
OGA (Output port G from Accumulator)
Instruction code D8 0 1 0 0 0 0 0 0 D0 0
2
0
8
0
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1 Grouping:
Operation:
(G)
(A)
Input/Output operation
Description: Outputs the contents of register A to port G.
POF (Power OFf1)
Instruction code D8 0 0 0 0 0 1 1 0 D0 1
2
0
0
D
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1 Grouping:
Operation:
RAM back-up
Other operation
Description: Puts the system in RAM back-up state
RAR (Rotate Accumulator Right)
Instruction code D8 0 0 0 0 1 1 1 0 D0 1
2
0
1
D
Number of words
16
Number of cycles 1
Flag CY 0/1
Skip condition -
1 Grouping:
Operation:
CY
A3A2A1A0
Arithmetic operation
Description: Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right.
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4286 Group
RB j (Reset Bit)
Instruction code D8 0 0 1 0 0 1 1 j1 D0 j0
2
0
4
C +j 16
Number of words 1 Grouping:
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(Mj(DP)) j = 0 to 3
0
Bit operation
Description: Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
RC (Reset Carry flag)
Instruction code D8 0 0 0 0 0 0 1 1 D0 0
2
0
0
6
Number of words
16
Number of cycles 1
Flag CY 0
Skip condition -
1 Grouping:
Operation:
(CY)
0
Arithmetic operation
Description: Clears (0) to carry flag CY.
RCAR (Reset CAR flag)
Instruction code D8 0 1 0 0 0 0 1 1 D0 0
2
0
8
6
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1 Grouping:
Operation:
(CAR)
0
Carrier wave control operation
Description: Clears (0) to port CARR output flag.
RD (Reset port D specified by register Y)
Instruction code D8 0 0 0 0 1 0 1 0 D0 0
2
0
1
4
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1 Grouping:
Operation:
(D(Y)) 0 However, (Y) = 0 to 7
Input/Output operation
Description: Clears (0) to a bit of port D specified by register Y (high-impedance state).
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4286 Group
RT (ReTurn from subroutine)
Instruction code D8 0 0 1 0 0 0 1 0 D0 0
2
0
4
4
Number of words
16
Number of cycles 2
Flag CY -
Skip condition -
1 Grouping:
Operation:
(SP) (PC)
(SP) - 1 (SK(SP))
Return operation
Description: Returns from subroutine to the routine called the subroutine.
RTS (ReTurn form subroutine and Skip)
Instruction code D8 0 0 1 0 0 0 1 0 D0 1
2
0
4
5
Number of words
16
Number of cycles 2
Flag CY -
Skip condition Skip at uncondition
1 Grouping:
Operation:
(SP) (PC)
(SP) - 1 (SK(SP))
Return operation
Description: Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition.
SB j (Set Bit)
Instruction code D8 0 0 1 0 1 1 1 j1 D0 j0
2
0
5
C +j 16
Number of words 1 Grouping:
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(Mj(DP)) j = 0 to 3
1
Bit operation
Description: Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
SC (Set Carry flag)
Instruction code D8 0 0 0 0 0 0 1 1 D0 1
2
0
0
7
Number of words
16
Number of cycles 1
Flag CY 1
Skip condition -
1 Grouping:
Operation:
(CY)
1
Arithmetic operation
Description: Sets (1) to carry flag CY.
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4286 Group
SCAR (Set CAR flag)
Instruction code D8 0 1 0 0 0 0 1 1 D0 1
2
0
8
7
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1 Grouping:
Operation:
(CAR)
1
Carrier wave control operation
Description: Sets (1) to port CARR output flag (CAR).
SD (Set port D specified by register Y)
Instruction code D8 0 0 0 0 1 0 1 0 D0 1
2
0
1
5
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1 Grouping:
Operation:
(D(Y)) 1 (Y) = 0 to 7
Input/Output operation
Description: Sets (1) to a bit of port D specified by register Y.
SEA n (Skip Equal, Accumulator with immediate data n)
Instruction code D8 0 0 Operation: 0 1 0 0 1 1 0 1 0 1 0 D0 1
2
0 0
2 B
5 n
Number of words
16
Number of cycles 2
Flag CY -
Skip condition (A) = n, n = 0 to 15
2 Grouping:
n3 n2 n1 n0
2
16
Comparison operation
(A) = n ? n = 0 to 15
Description: Skips the next instruction when the contents of register A is equal to the value n in the immediate field.
SEAM (Skip Equal, Accumulator with Memory)
Instruction code D8 0 0 0 1 0 0 1 1 D0 0
2
0
2
6
Number of words
16
Number of cycles 1
Flag CY -
Skip condition (A) = (M(DP))
1 Grouping:
Operation:
(A) = (M(DP)) ?
Comparison operation
Description: Skips the next instruction when the contents of register A is equal to the contents of M(DP).
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4286 Group
SNZP (Skip if Non Zero condition of Power down flag)
Instruction code D8 0 0 0 0 0 0 0 1 D0 1
2
0
0
3
Number of words
16
Number of cycles 1
Flag CY -
Skip condition (P) = 1
1 Grouping:
Operation:
(P) = 1 ?
Other operation
Description: Skips the next instruction when P flag is "1". After skipping, P flag remains unchanged.
SNZT1 (Skip if Non Zero condition of Timer 1 underflow flag)
Instruction code D8 0 0 1 0 0 0 0 1 D0 0
2
0
4
2
Number of words
16
Number of cycles 1
Flag CY -
Skip condition (T1F) = 1
1 Grouping:
Operation:
(T1F) = 1 ? (T1F) 0
Timer operation
Description: Clears T1F flag and skips the next instruction when the contents of T1F flag is "1."
SNZT2 (Skip if Non Zero condition of Timer 2 interrupt request flag)
Instruction code D8 0 0 1 0 1 0 0 1 D0 0
2
0
5
2
Number of words
16
Number of cycles 1
Flag CY -
Skip condition (T2F) = 1
1 Grouping:
Operation:
(T2F) = 1 ? (T2F) 0
Timer operation
Description: Clears T2F flag and skips the next instruction when the contents of T2F flag is "1."
SZBj (Skip if Zero, Bit)
Instruction code D8 0 0 0 1 0 0 0 j1 D0 j0
2
0
2
j
Number of words
16
Number of cycles 1
Flag CY -
Skip condition (Mj(DP)) = 0 j = 0 to 3
1 Grouping:
Operation:
(Mj(DP)) = 0 ? j = 0 to 3
Bit operation
Description: Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of M(DP) is "0."
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4286 Group
SZC (Skip if Zero, Carry flag)
Instruction code D8 0 0 0 1 0 1 1 1 D0 1
2
0
2
F
Number of words
16
Number of cycles 1
Flag CY -
Skip condition (CY) = 0
1 Grouping:
Operation:
(CY) = 0 ?
Arithmetic operation
Description: Skips the next instruction when the contents of carry flag CY is "0."
SZD (Skip if Zero, port D specified by register Y)
Instruction code D8 0 0 Operation: 0 0 0 0 1 1 0 0 0 1 1 0 0 1 D0 0 1
2
0 0
2 2
4 B
Number of words
16
Number of cycles 2
Flag CY -
Skip condition (D(Y)) = 0
(Y) = 0 to 7
2
2
16
(D(Y)) = 0 ? (Y) = 0 to 7
Grouping:
Input/Output operation
Description: Skips the next instruction when a bit of port D specified by register Y is "0."
T1AB (Transfer data to timer 1 and register R1 from Accumulator and register B)
Instruction code D8 0 0 1 0 0 0 1 1 D0 1
2
0
4
7
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1 Grouping:
Operation:
at timer 1 stop (V10=0) (B), (R13-R10) (R17-R14) (T17-T14) (B), (T13-T10) at timer 1 operating (V10=1) (R17-R14) (B), (R13-R10)
Timer operation
(A) (A) (A)
Description: At timer 1 stop (V10 = 0), transfers the contents of register A and register B to timer 1 and reload register R1. At timer 1 operating (V10 = 1), transfers the contents of register A and register B to reload register R1.
T2AB (Transfer data to timer 2 and register R2L from Accumulator and register B)
Instruction code D8 0 1 0 0 0 1 0 0 D0 0
2
0
8
8
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1 Grouping:
Operation:
(R2L7-R2L4) (B) (R2L3-R2L0) (A) (T27-T24) (B) (A) (T23-T20)
Timer operation
Description: Transfers the contents of registers A and B to timer 2 and timer 2 reload register R2L.
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4286 Group
T2HAB (Transfer data to register R2H Accumulator from register B)
Instruction code D8 0 1 0 0 0 1 0 0 D0 1
2
0
8
9 16
Number of words 1 Grouping:
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(R2H7-R2H4) (R2H3-R2H0)
(B) (A)
Timer operation
Description: Transfers the contents of register A and register B to reload register R2H.
T2R2L (Transfer data to timer 2 from register R2L)
Instruction code D8 0 0 1 0 1 0 0 1 D0 1
2
0
5
3
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1 Grouping:
Operation:
(T27-T24) (T23-T20)
(R2L7-R2L4) (R2L3-R2L0)
Timer operation
Description: Transfers the contents of reload register R2L to timer 2.
TAB (Transfer data to Accumulator from register B)
Instruction code D8 0 0 0 0 1 1 1 1 D0 0
2
0
1
E
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1 Grouping:
Operation:
(A)
(B)
Register to register transfer
Description: Transfers the contents of register B to register A.
TAB1 (Transfer data to Accumulator and register B from timer 1)
Instruction code D8 0 0 1 0 1 0 1 1 D0 1
2
0
5
7
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1 Grouping:
Operation:
(B) (A)
(T17-T14) (T13-T10)
Timer operation
Description: Transfers the contents of timer 1 to registers A and B.
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4286 Group
TAB2 (Transfer data to Accumulator and register B from timer 2)
Instruction code D8 0 0 1 0 0 0 0 0 D0 0
2
0
4
0
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1 Grouping:
Operation:
(B) (A)
(T27-T24) (T23-T20)
Timer operation
Description: Transfers the contents of timer 2 to registers A and B.
TABE (Transfer data to Accumulator and register B from register E)
Instruction code D8 0 0 0 1 0 1 0 1 D0 0
2
0
2
A
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1 Grouping:
Operation:
(B) (A)
(ER7-ER4) (ER3-ER0)
Register to register transfer
Description: Transfers the contents of register E to registers A and B.
TABP p (Transfer data to Accumulator and register B from Program memory in page p)
Instruction code D8 0 1 0 0 1 D0 p3 p2 p1 p0
2
0
9
p
Number of words
16
Number of cycles 3
Flag CY
Skip condition
Operation:
SK(SP)) (PC) , (SP) (SP) + 1 (PCH) p, (Note), (PC L) (DR2 -DR0, A3-A0) When URS = 0, (ROM(PC))3 to 0 (B) (ROM(PC))7 to 4, (A) When URS = 1, (CY) (ROM(PC))8 (B) (ROM(PC))7 to 4, (A) (ROM(PC))3 to 0 (SP) (SP) - 1, (PC) (SK(SP))
- - 0/1 Grouping: Arithmetic operation Description: Transfers bits 7 to 4 to register B and bits 3 to 0 to register A when URS flag is cleared to "0". These bits 7 to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0) specified by registers A and D in page p. Transfers bit 8 ROM pattern is transferred CY=0/1: to flag CY when URS flag is set to "1". (after the URSC instruction is executed). (One of stack is used when the TABP p instruction is executed.) p is 0 to 15. Note: 1
TAMj (Transfer data to Accumulator from Memory)
Instruction code D8 0 0 1 1 0 0 1 j1 D0 j0
2
0
6
4 +j 16
Number of words 1 Grouping:
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(A) (M(DP)) (X) (X)EXOR(j) j = 0 to 3
RAM to register transfer
Description: After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
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4286 Group
TAY (Transfer data to Accumulator from register Y)
Instruction code D8 0 0 0 0 1 1 1 1 D0 1
2
0
1
F
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A)
(Y)
Grouping: Register to register transfer Description: Transfers the contents of register Y to register A.
TBA (Transfer data to register B from Accumulator)
Instruction code D8 0 0 0 0 0 1 1 1 D0 0
2
0
0
E
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1 Grouping:
Operation:
(B)
(A)
Register to register transfer
Description: Transfers the contents of register A to register B.
TDA (Transfer data to register D from Accumulator)
Instruction code D8 0 0 0 1 0 1 0 0 D0 1
2
0
2
9
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1 Grouping:
Operation:
(DR2-DR0)
(A2-A0)
Register to register transfer
Description: Transfers the contents of register A to register D.
TEAB (Transfer data to register E from Accumulator and register B)
Instruction code D8 0 0 0 0 1 1 0 1 D0 0
2
0
1
A
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1 Grouping:
Operation:
(ER7-ER4) (ER3-ER0)
(B) (A)
Register to register transfer
Description: Transfers the contents of register A and register B to register E.
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4286 Group
TLOA (Transfer data to register LO from Accumulator)
Instruction code D8 0 0 1 0 1 1 0 0 D0 0
2
0
5
8
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1 Grouping:
Operation:
(LO1, LO0)
(A1, A0)
Other operation
Description: Transfers the contents of register A to logic operation selection register LO.
TPU0A (Transfer data to register PU0 from Accumulator)
Instruction code D8 0 1 0 0 0 1 1 1 D0 1
2
0
8
F
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1 Grouping:
Operation:
(PU03-PU00)
(A3-A0)
Other operation
Description: Transfers the contents of register A to pullup control register PU0.
TPU1A (Transfer data to register PU1 from Accumulator)
Instruction code D8 0 1 0 0 0 1 1 1 D0 0
2
0
8
E
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(PU13-PU10)
(A3-A0)
Grouping: Other operation Description: Transfers the contents of register A to pullup control register PU1.
TPU2A (Transfer data to register PU2 from Accumulator)
Instruction code D8 0 1 0 0 0 1 1 0 D0 1
2
0
8
D
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1 Grouping:
Operation:
(PU23-PU20)
(A3-A0)
Other operation
Description: Transfers the contents of register A to pullup control register PU2.
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4286 Group
TV1A (Transfer data to register V1 from Accumulator)
Instruction code D8 0 0 1 0 1 0 1 1 D0 1
2
0
5
B
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1 Grouping:
Operation:
(V12-V10)
(A2-A0)
Timer operation
Description: Transfers the contents of register A to register V1.
TV2A (Transfer data to register V2 from Accumulator)
Instruction code D8 0 0 1 0 1 1 0 1 D0 0
2
0
5
A
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1 Grouping:
Operation:
(V23-V20)
(A3-A0)
Timer operation
Description: Transfers the contents of register A to register V2.
TYA (Transfer data to regiser Y from Accumulator)
Instruction code D8 0 0 0 0 0 1 1 0 D0 0
2
0
0
C
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1 Grouping:
Operation:
(Y)
(A)
Register to register transfer
Description: Transfers the contents of register A to register Y.
URSC (Sets Upper ROM Code reference enable flag)
Instruction code D8 0 1 0 0 0 0 0 1 D0 0
2
0
8
2
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1 Grouping:
Operation:
(URS)
1
Other operation
Description: Sets the most significant ROM code reference enable flag (URS) to "1."
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4286 Group
WRST (Watchdog timer ReSeT)
Instruction code D8 0 0 0 0 0 1 1 1 D0 1
2
0
0
F
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1 Grouping:
Operation:
(WDF1)
0
Other operation
Description: Initializes the watchdog timer flag (WDF1).
XAM j (eXchange Accumulator and Memory data)
Instruction code D8 0 0 1 1 0 0 0 j1 D0 j0
2
0
6
j
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1 Grouping:
Operation:
(A) (M(DP)) (X) (X)EXOR(j) j = 0 to 3
RAM to register transfer
Description: After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
XAMD j (eXchange Accumulator and Memory data and Decrement register Y and skip)
Instruction code D8 0 0 1 1 0 1 1 j1 D0 j0
2
0
6
C +j 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition (Y) = 15
Operation:
(A) (M(DP)) (X) (X)EXOR(j) j = 0 to 3 (Y) - 1 (Y)
Grouping: RAM to register transfer Description: After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. D0 Number of words 1 Grouping: Number of cycles 1 Flag CY - Skip condition (Y) = 0
XAMI j (eXchange Accumulator and Memory data and Increment register Y and skip)
Instruction code D8 0 0 1 1 0 1 0 j1 j0
2
0
6
8 +j 16
Operation:
(A) (M(DP)) (X) (X)EXOR(j) j = 0 to 3 (Y) + 1 (Y)
RAM to register transfer
Description: After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped.
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4286 Group
INSTRUCTION CODE TABLE
D8-D4 Hex.
notation
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 00 NOP BA 01 BLA CLD 02 SZB 0 SZB 1 SZB 2 SNZP INY RD SD RC SC SZB 3 SZD 03 BL BL 04 05 06 XAM 0 XAM 1 XAM 2 07 BML BML BML BML BML BML BML RCAR BML SCAR T2AB
T2HAB
10000 11000 10111 11111 10-17 18-1F BM BM BM B B B B
D3-D0
08
09
0A A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 9 A 10 A 11 A 12 A 13 A 14 A 15
0B LA 0 LA 1 LA 2 LA 3 LA 4 LA 5 LA 6 LA 7 LA 8 LA 9 LA 10 LA 11 LA 12 LA 13 LA 14 LA 15
0C LXY 0,0 LXY 0,1 LXY 0,2 LXY 0,3 LXY 0,4 LXY 0,5 LXY 0,6 LXY 0,7 LXY 0,8 LXY 0,9 LXY 0,10 LXY 011 LXY 0,12 LXY 0,13 LXY 0,14 LXY 0,15
0D LXY 1,0 LXY 1,1 LXY 1,2 LXY 1,3 LXY 1,4 LXY 1,5 LXY 1,6 LXY 1,7 LXY 1,8 LXY 1,9 LXY 1,10 LXY 1,11 LXY 1,12 LXY 1,13 LXY 1,14 LXY 1,15
0E LXY 2,0 LXY 2,1 LXY 2,2 LXY 2,3 LXY 2,4 LXY 2,5 LXY 2,6 LXY 2,7 LXY 2,8 LXY 2,9 LXY 2,10 LXY 2,11 LXY 2,12 LXY 2,13 LXY 2,14 LXY 2,15
0F LXY 3,0 LXY 3,1 LXY 3,2 LXY 3,3 LXY 3,4 LXY 3,5 LXY 3,6 LXY 3,7 LXY 3,8 LXY 3,9 LXY 3,10 LXY 3,11 LXY 3,12 LXY 3,13 LXY 3,14 LXY 3,15
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
0 1 2 3 4 5 6 7 8 9 A B C D E F
TAB2 BMLA LGOP
SNZT1 SNZT2
OGA TABP 0 TABP 1 URSC TABP 2 TABP 3 OEA TABP 4 TABP 5 TABP 6 TABP 7 TABP 8 TABP 9 TABP 10 TABP 11 TABP 12
TPU2A TABP
BL BL
T2R2L XAM
3 RT RTS IAE T1AB TAB1 TLOA CCK TV2A TAM 0 TAM 1 TAM 2 TAM 3
BM BM BM BM BM BM BM
BL BL BL
B B B B B
SEAn SEAM
DEY IAG CCK2 TDA
BL BL BL BL BL
XAMI BML 0 XAMI BML 1 XAMI BML 2 XAMI BML 3 XAMD BML 0 XAMD BML 1 XAMD BML 2 XAMD BML 3
B B B B B B B
AM AMC TYA
TEAB TABE
BM BM BM BM BM BM
TV1A RB 0 RB 1 RB 2 RB 3 SB 0 SB 1 SB 2 SB 3
CMA RAR CCK4 TAB CLVD
BL
POF TBA
BL
13
TPU1A TABP
BL BL
14
TPU0A
WRST TAY
SZC
TABP 15
The above table shows the relationship between machine language codes and machine language instructions. D3-D0 show the low-order 4 bits of the machine language code, and D8-D4 show the high-order 5 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use the code marked "-." The codes for the second word of a two-word instruction are described below.
BL BML BA BLA BMLA SEA SZD
The second word 1 1aaa aaaa 1 0aaa aaaa 1 1aaa aaaa 1 1aaa pppp 1 0aaa pppp 0 1011 nnnn 0 0010 1011 page 47 of 64
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4286 Group
MACHINE INSTRUCTIONS (INDEX BY FUNCTION)
Number of words
Parameter
Instruction code Mnemonic D8 D7 D6 D5 D4 D3 D2 D1 D0 TAB TBA TAY TYA TEAB TABE TDA LXY x, y 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 0 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 0 1 1 0 0 0 1 0 0 0 1
Hexadecimal notation
Number of cycles
Function
Type of instructions
01 00 01 00 01 02 02
E E F C A A 9
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
(A) (B) (B) (A) (A) (Y) (Y) (A) (ER7-ER4) (B) (ER3-ER0) (A) (B) (ER7-ER4) (A) (ER3-ER0) (DR2-DR0) (A2-A0) (X) x, x = 0 to 3 (Y) y, y = 0 to 15
Register to register transfer
x1 x0 y3 y2 y1 y0
0Cy +x
RAM addresses
INY
0
0
0
0
1
0
0
1
1
01
3
1
1
(Y) (Y) + 1
DEY
0
0
0
0
1
0
1
1
1
017
1
1
(Y) (Y) - 1
TAM j
0
0
1
1
0
0
1
j1
j0
06
4 +j
1
1
(A) (M(DP)) (X) (X) EXOR(j) j = 0 to 3
XAM j
0
0
1
1
0
0
0
j1
j0
06
j
1
1
(A) (M(DP)) (X) (X) EXOR(j) j = 0 to 3
RAM to register transfer
XAMD j
0
0
1
1
0
1
1
j1
j0
06
C +j
1
1
(A) (M(DP)) (X) (X) EXOR(j) j = 0 to 3 (Y) (Y) - 1
XAMI j
0
0
1
1
0
1
0
j1
j0
06
8 +j
1
1
(A) (M(DP)) (X) (X) EXOR(j) j = 0 to 3 (Y) (Y) + 1
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4286 Group
Skip condition
Carry flag CY
Detailed description
- - - - - - - Continuous description
- - - - - - - -
Transfers the contents of register B to register A. Transfers the contents of register A to register B. Transfers the contents of register Y to register A. Transfers the contents of register A to register Y. Transfers the contents of registers A and B to register E. Transfers the contents of register E to registers A and B. Transfers the contents of register A to register D. Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y. When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continuously are skipped.
(Y) = 0
-
Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped.
(Y) = 15
-
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped.
-
-
After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
-
-
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
(Y) = 15
-
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped.
(Y) = 0
-
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped.
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4286 Group
MACHINE INSTRUCTIONS (CONTINUED)
Number of words
Parameter
Instruction code Mnemonic D8 D7 D6 D5 D4 D3 D2 D1 D0 LA n 0 1 0 1 1 n3 n2 n1 n0
Hexadecimal notation
Number of cycles
Function
Type of instructions
0Bn
1
1
(A) n n = 0 to 15
TABP p
0
1
0
0
1
p3 p2 p1 p0
09
p
1
3
(SK(SP)) (PC) (SP) (SP) + 1 (PCH) p (Note) (PCL) (DR2-DR0, A3-A0) When URS=0, (B) (ROM(PC))7 to 4 (A) (ROM(PC))3 to 0 When URS=1, (CY) (ROM(PC))8 (B) (ROM(PC))7 to 4 (A) (ROM(PC))3 to 0 (SP) (SP) - 1 (PC) (SK(SP))
AM
0
0
0
0
0
1
0
1
0
00
A
1
1
(A) (A) + (M(DP))
Arithmetic operation
AMC
0
0
0
0
0
1
0
1
1
00
B
1
1
(A) (A) + (M(DP))+ (CY) (CY) Carry
An
0
1
0
1
0
n3 n2 n1 n0
0An
1
1
(A) (A) + n n = 0 to 15
SC RC SZC CMA RAR LGOP
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 1
0 0 1 0 0 0
0 0 0 1 1 0
0 0 1 1 1 0
1 1 1 1 1 0
1 1 1 0 0 0
1 0 1 0 1 1
00 00 02 01 01 04
7 6 F C D 1
1 1 1 1 1 1
1 1 1 1 1 1
(CY) 1 (CY) 0 (CY) = 0 ? (A) (A) CY A3A2A1A0 Logic operation instruction XOR, OR, AND
Note: p is 0 to 15.
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4286 Group
Skip condition
Carry flag CY
Detailed description
Continuous description
-
Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously are skipped.
-
-
Transfers bits 7 to 4 to register B and bits 3 to 0 to register A when URS flag is cleared to "0." These bits 7 to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0) specified by registers A and D in page p.
0/1 Transfers bit 8 of ROM pattern is transferred to flag CY when URS flag is set to "1" (after the URSC instruction is executed). (One of stack is used when the TABP p instruction is executed.)
-
-
Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged.
-
0/1 Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY.
Overflow = 0
-
Adds the value n in the immediate field to register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation.
- - (CY) = 0 - - -
1 0 - -
Sets (1) to carry flag CY. Clears (0) to carry flag CY. Skips the next instruction when the contents of carry flag CY is "0." Stores the one`s complement for register A`s contents in register A.
0/1 Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right. - Executes the logic operation selected by logic operation selection register LO between the contents of register A and register E, and stores the result in register A.
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4286 Group
MACHINE INSTRUCTIONS (CONTINUED)
Number of words
Parameter
Instruction code Mnemonic D8 D7 D6 D5 D4 D3 D2 D1 D0 SB j 0 0 1 0 1 1 1 j1 j0
Hexadecimal notation
Number of cycles
Function
Type of instructions
05
C +j
1
1
(Mj(DP)) 1 j = 0 to 3
Bit operation
RB j
0
0
1
0
0
1
1
j1
j0
04
C +j
1
1
(Mj(DP)) 0 j = 0 to 3
SZB j
0
0
0
1
0
0
0
j1
j0
02
j
1
1
(Mj(DP)) = 0 ? j = 0 to 3
SEAM
0 0 0
0 0 1 1
0 0 0
1 1 1
0 0 1
0 0
1 1
1 0
0 1
02 02
6 5
1 2
1 2
(A) = (M(DP)) ? (A) = n ? n = 0 to 15
Comparison
operation
SEA n
n3 n2 n1 n0
0Bn 1 8 +a a 1 1 (PCL) a6-a0
Ba
1
a6 a5 a4 a3 a2 a1 a0
BL p, a
0
0
0
1
1
p3 p2 p1 p0
03
p
2
2
(PCH) p (PCL) a6-a0 (Note)
Branch operation
1
1
a6 a5 a4 a3 a2 a1 a0
18 +a
a
BA a
0 1
0 1
0
0
0
0
0
0
1
00 18 +a
1 a
2
2
(PCL) (a6-a4, A3-A0)
a6 a5 a4 a3 a2 a1 a0
BLA p, a
0 1
0 1
0
0
1
0
0
0
0
01 18 +a
0 p
2
2
(PCH) p (PCL) (a6-a4, A3-A0) (Note)
a6 a5 a4 p3 p2 p1 p0
Note: p is 0 to 15.
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4286 Group
Skip condition
Carry flag CY
Detailed description
-
-
Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
-
-
Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
(Mj(DP)) = 0 j = 0 to 3 (A) = (M(DP)) (A) = n n = 0 to 15
-
Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of M(DP) is "0."
- -
Skips the next instruction when the contents of register A is equal to the contents of M(DP). Skips the next instruction when the contents of register A is equal to the value n in the immediate field.
-
-
Branch within a page : Branches to address a in the identical page.
-
-
Branch out of a page : Branches to address a in page p.
-
-
Branch within a page : Branches to address (a6 a5 a4 A3 A2 A1 A0) determined by replacing the loworder 4 bits of the address a in the identical page with register A.
-
-
Branch out of a page : Branches to address (a6 a5 a4 A3 A2 A1 A0) determined by replacing the loworder 4 bits of the address a in page p with register A.
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4286 Group
MACHINE INSTRUCTIONS (CONTINUED)
Number of words
Parameter
Instruction code Mnemonic D8 D7 D6 D5 D4 D3 D2 D1 D0 BM a 1 0 a6 a5 a4 a3 a2 a1 a0
Hexadecimal notation
Number of cycles
Function
Type of instructions
1
a
a
1
1
(SK(SP)) (PC) (SP) (SP) + 1 (PCH) 2 (PCL) a6-a0
Subroutine operation
BML p, a
0
0
1
1
1
p3 p2 p1 p0
07
p
2
2
(SK(SP)) (PC) (SP) (SP) + 1 (PCH) p
1
0
a6 a5 a4 a3 a2 a1 a0
1aa
(PCL) a6-a0 (Note)
BMLA p, a 0 1
0 0
1
0
1
0
0
0
0
05 1a
0 p
2
2
(SK(SP)) (PC) (SP) (SP) + 1 (PCH) p (PCL) (a6-a4, A3-A0) (Note)
a6 a5 a4 p3 p2 p1 p0
Return operation
RT
0
0
1
0
0
0
1
0
0
04
4
1
2
(SP) (SP) - 1 (PC) (SK(SP))
RTS
0
0
1
0
0
0
1
0
1
04
5
1
2
(SP) (SP) - 1 (PC) (SK(SP))
T1AB
0
0
1
0
0
0
1
1
1
047
1
1
at timer 1 stop (V10=0) (R17-R14) (B), (R13-R10) (A) (T17-T14) (B), (T13-T10) (A) at timer 1 operating (V10=1) (R17-R14) (B), (R13-R10) (A)
TAB1
0
0
1
0
1
0
1
1
1
057
1
1
(B) (T17-T14) (A) (T13-T10)
Timer operation
TV1A SNZT1
0 0
0 0
1 1
0 0
1 0
1 0
0 0
1 1
1 0
05B 042
1 1
1 1
(V12-V10) (A2-A0) (T1F) = 1 ? (T1F) 0
T2AB
0
1
0
0
0
1
0
0
0
088
1
1
(R2L7-R2L4) (B) (R2L3-R2L0) (A) (T27-T24) (B), (T23-T20) (A)
Note : p is 0 to 15.
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4286 Group
Skip condition
Carry flag CY
Detailed description
-
-
Call the subroutine in page 2 : Calls the subroutine at address a in page 2.
-
-
Call the subroutine : Calls the subroutine at address a in page p.
-
-
Call the subroutine : Calls the subroutine at address (a6 a5 a4 A3 A2 A1 A0) determined by replacing the low-order 4 bits of address a in page p with register A.
-
-
Returns from subroutine to the routine called the subroutine.
Skip at uncondition
-
Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition.
-
-
At timer 1 stop (V10 = 0), transfers the contents of register A and register B to timer 1 and reload register R1. At timer 1 operating (V10 = 1), transfers the contents of register A and register B to reload register R1.
-
-
Transfers the contents of timer 1 to registers A and B.
- (T1F) = 1
- -
Transfers the contents of register A to registers V1. Clears T1F flag and skips the next instruction when the contents of T1F flag is "1."
-
-
Transfers the contents of register A and register B to timer 2 and reload register R2L.
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4286 Group
MACHINE INSTRUCTIONS (CONTINUED)
Number of words
Parameter
Instruction code Mnemonic D8 D7 D6 D5 D4 D3 D2 D1 D0 TAB2 TV2A 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 0 1 0 0 0 0 0 1 1 0 0 0
Hexadecimal notation
Number of cycles
Function
Type of instructions
040 05A 052
1 1 1
1 1 1
(B) (T27-T24), (A) (T23-T20) (V23-V20) (A3-A0) (T2F) = 1 ? (T2F) 0
Timer operation
SNZT2
T2HAB
0
1
0
0
0
1
0
0
1
089
1
1
(R2H7-R2H4) (B) (R2H3-R2H0) (A)
T2R2L
0
0
1
0
1
0
0
1
1
053
1
1
(T27-T24) (R2L7-R2L4) (T23-T20) (R2L3-R2L0)
control operation
Carrier wave
SCAR RCAR
0 0
1 1
0 0
0 0
0 0
0 0
1 1
1 1
1 0
087 086
1 1
1 1
(CAR) 1 (CAR) 0
CLD RD
0 0
0 0
0 0
0 0
1 1
0 0
0 1
0 0
1 0
011 014
1 1
1 1
(D) 0 (D(Y)) 0 (Y) = 0 to 7
SD
0
0
0
0
1
0
1
0
1
015
1
1
(D(Y)) 1 (Y) = 0 to 7
SZD
0 0
0 0 1 0 1 0
0 0 0 1 0 0
1 1 0 0 0 1
0 0 0 1 0 0
0 1 0 0 0 1
1 0 1 1 0 0
0 1 0 1 0 0
0 1 0 0 0 0
024 02B 084 056 080 028
2
2
(D(Y)) = 0 ? (Y) = 0 to 7
Input/Output operation
OEA IAE OGA IAG
0 0 0 0
1 1 1 1
1 1 1 1
(E1, E0) (A1, A0) (A2-A0) (E2-E0) (G) (A) (A) (G)
Rev.1.00 Aug 06, 2008 REJ03B0251-0100
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4286 Group
Skip condition
Carry flag CY
Detailed description
- - (T2F) = 1
- - -
Transfers the contents of timer 2 to registers A and B. Transfers the contents of register A to registers V2. Clears T2F flag and skips the next instruction when the contents of T2F flag is "1."
-
-
Transfers the contents of register A and register B to reload register R2H.
-
-
Transfers the contents of reload register R2L to timer 2.
- -
- -
Sets (1) to port CARR output flag (CAR). Clears (0) to port CARR output flag (CAR).
- -
- -
Clears (0) to port D (high-impedance state). Clears (0) to a bit of port D specified by register Y (high-impedance state).
-
-
Sets (1) to a bit of port D specified by register Y.
(D(Y)) = 0 (Y) = 0 to 7
-
Skips the next instruction when a bit of port D specified by register Y is "0."
- - - -
- - - -
Outputs the contents of register A to port E. Transfers the contents of port E to register A. Outputs the contents of register A to port G. Transfers the contents of port G to register A.
Rev.1.00 Aug 06, 2008 REJ03B0251-0100
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4286 Group
Number of words
Parameter
Instruction code Mnemonic D8 D7 D6 D5 D4 D3 D2 D1 D0 NOP POF 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1
Hexadecimal notation
Number of cycles
Function
Type of instructions
000 00 D
1 1
1 1
(PC) (PC) + 1 RAM back-up
SNZP
0
0
0
0
0
0
0
1
1
00
3
1
1
(P) = 1 ?
Other operation
CCK CCK2 CCK4 CLVD TLOA URSC TPU0A TPU1A TPU2A WRST
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 1 1 1 1 0
1 0 0 0 1 0 0 0 0 0
0 0 1 1 0 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0
1 1 1 1 1 0 1 1 1 1
0 0 1 1 0 0 1 1 1 1
0 0 0 1 0 1 1 1 0 1
1 1 1 0 0 0 1 0 1 1
05 01 02 02 05 08 08 08 08 00
9 9 D E 8 2 F E D F
1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1
STCK changes to f(XIN) STCK changes to f(XIN)/2 STCK changes to f(XIN)/4 Reset occurrence voltage 1.5V 1.7V (LO1, LO0) (A1, A0) (URS) 1 (PU03-PU00) (A3-A0) (PU13-PU10) (A3-A0) (PU23-PU20) (A3-A0) (WDF1) 0
Rev.1.00 Aug 06, 2008 REJ03B0251-0100
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4286 Group
Skip condition
Carry flag CY
Detailed description
- -
- -
No operation Puts the system in RAM back-up state.
(P) = 1
-
Skips the next instruction when P flag is "1". After skipping, P flag remains unchanged.
- - - - - - - - - -
- - - - - - - - - -
System clock (STCK) changes to f(XIN) from f(XIN)/8. System clock (STCK) changes to f(XIN) /2from f(XIN)/8. System clock (STCK) changes to f(XIN) /4from f(XIN)/8. Change detection voltage from 1.5V to 1.7V (Ta = 25C, Typ). Transfers the contents of register A to the logic operation selection register LO. Sets the most significant ROM code reference enable flag (URS) to "1." Transfers the contents of register A to register PU0. Transfers the contents of register A to register PU1. Transfers the contents of register A to register PU2. Initializes the watchdog timer flag (WDF1).
Rev.1.00 Aug 06, 2008 REJ03B0251-0100
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4286 Group
REGISTER STRUCTURE
Timer control register V1 V12 V11 V10 Carrier wave output auto-control bit Timer 1 count source selection bit Timer 1 control bit 0 1 0 1 0 1 at reset : 0002 at RAM back-up : 0002 W Auto-control output by timer 1 is invalid Auto-control output by timer 1 is valid Carrier wave output (CARRY) Bit 5 of watchdog timer (WDT) Stop (Timer 1 state retained) Operating at reset : 00002 0 1 0 1 0 1 0 1 at RAM back-up : 00002 W
Timer control register V2 V23 V22 V21 V20 Carrier wave "H" interval expansion bit Carrier wave generation function control bit Timer 2 count source selection bit Timer 2 control bit
To expand "H" interval is invalid To expand "H" interval is valid (when V22=1 selected) Carrier wave generation function invalid Carrier wave generation function valid f(XIN) f(XIN)/2 Stop (Timer 2 state retained) Operating
Pull-down control register PU0 PU03 PU02 PU01 PU00 Ports G2, G3 pull-down transistor control bit Ports G0, G1 pull-down transistor control bit Port E1 pull-down transistor control bit Port E0 pull-down transistor control bit 0 1 0 1 0 1 0 1
at reset : 00002
at RAM back-up : state retained
W
Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid
Pull-down control register PU1 PU13 PU12 PU11 PU10 Port D7 pull-down transistor control bit Port D6 pull-down transistor control bit Port D5 pull-down transistor control bit Port D4 pull-down transistor control bit 0 1 0 1 0 1 0 1
at reset : 00002
at RAM back-up : state retained
W
Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid
Note: "W" represents write enabled.
Rev.1.00 Aug 06, 2008 REJ03B0251-0100
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4286 Group
Pull-down control register PU2 PU23 PU22 PU21 PU20 Port D3 pull-down transistor control bit Port D2 pull-down transistor control bit Port D1 pull-down transistor control bit Port D0 pull-down transistor control bit 0 1 0 1 0 1 0 1
at reset : 00002
at RAM back-up : state retained
W
Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid
Logic operation selection register LO
at reset : 002 LO1 LO0
at RAM back-up : 002 Logic operation function
W
LO1 Logic operation selection bits LO0
0 0 1 1
0 Exclusive logic OR operation (XOR) 1 OR operation (OR) 0 AND operation (AND) 1 Not available
Note: "W" represents write enabled.
Rev.1.00 Aug 06, 2008 REJ03B0251-0100
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4286 Group
ABSOLUTE MAXIMUM RATINGS
Symbol VDD VI VO Pd Topr Tstg Supply voltage Input voltage Output voltage Power dissipation Operating temperature range Storage temperature range Ta = 25 C Parameter Conditions -0.3 to 5 -0.3 to VDD+0.3 -0.3 to VDD+0.3 300 -40 to 85 -65 to 125 Ratings Unit V V V mW C C
RECOMMENDED OPERATING CONDITIONS
(Ta = -40 to 85 C, VDD = 1.8 V to 3.6 V, unless otherwise noted) Symbol VDD VRAM VSS VIH VIH VIL VIL Supply voltage RAM back-up voltage (at RAM back-up mode) Supply voltage "H" level input voltage Ports D, E, G "H" level input voltage XIN "L" level input voltage Ports D, E, G "L" level input voltage XIN VDD = 3.0 V VDD = 3.0 V VDD = 3.0 V VDD = 3.0 V VDD = 3.0 V VDD = 3.0 V VDD = 3.0 V VDD = 3.0 V VDD = 3.0 V VDD = 3.0 V VDD = 3.0 V VDD = 3.0 V 0.7VDD 0.8VDD 0 0 Parameter Conditions Limits Min. 1.8 1.1 0 VDD VDD 0.2VDD 0.2VDD -4 -24 -20 4 -2 -12 -10 2 4 2 1.1 Ta = 25 C Ta = 25 C Detection voltage (after CLVD instruction execution) TDET Reset occurrence/ Reset release Ta = 25 C When supply voltage passes the detected voltage at 50V/s. VDD = 0 2.2 V TPON Power-on reset circuit valid power source rising time Ta = -20 C to 85 C VDD = 0 2.2 V Ta = -40 C to 85 C Note: The average output current ratings are the average current value during 100 ms. 1.4 1.2 1.6 1.2 1.6 1.7 0.2 1.7 1.5 1.9 1.56 2.2 1.76 2.2 1.76 1.2 ms ms s V V Typ. Max. 3.6 3.6 Unit V V V V V V V mA mA mA mA mA mA mA mA MHz MHz
IOH(peak) "H" level peak output current Ports D, E1, G IOH(peak) "H" level peak output current Port E0 IOH(peak) "H" level peak output current CARR IOL(peak) "L" level peak output current CARR IOH(avg) "H" level average output current Ports D, E1, G IOH(avg) "H" level average output current Port E0 IOH(avg) "H" level average output current CARR IOL(avg) "L" level average output current CARR f(XIN)
when STCK = f(XIN)/8, f(XIN)/4, f(XIN)/2 selected Ceramic resonance clock frequency Ceramic resonance when STCK = f(XIN) selected Detection voltage (before CLVD instruction execution) Reset occurrence Reset release
VDET
Voltage drop detection circuit low voltage determination time
1 100
Rev.1.00 Aug 06, 2008 REJ03B0251-0100
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4286 Group
ELECTRICAL CHARACTERISTICS
(Ta = -40 C to 85 C, VDD = 3 V, unless otherwise noted) Symbol VOL VOL VOH VOH VOH VOH IIL IIH IOZ Parameter "L" level output voltage Port CARR "L" level output voltage XOUT "H" level output voltage Ports D, E1, G "H" level output voltage Port E0 "H" level output voltage CARR "H" level output voltage XOUT "L" level input current Ports D, E, G "H" level input current Ports E0, E1 Test conditions IOL = 2 mA IOL = 0.2 mA IOH = -2 mA IOH = -12 mA IOH = -10 mA IOH = -0.2 mA VI = VSS VI = VDD Pull-down transistor in off-state Output current at off-state Ports D, E0, E1, G VO = VSS f(XIN) = 4.0 MHz Supply current (when operating) IDD Supply current (at RAM back-up) RPH ROSC Pull-down resistor value Ports D, G, E Feedback resistor value between XIN-XOUT f(XIN) = 2.0 MHz f(XIN) = 1.0 MHz f(XIN) = 500 kHz Ta = 25 C VI = 3V 75 700 400 350 300 250 1 0.1 150 -1 800 700 600 500 3 0.5 300 3200 2.1 1.5 1.0 2.1 -1 1 Limits Min. Typ. Max. 0.9 0.9 Unit V V V V V V A A
A A A A A A A k k
BASIC TIMING DIAGRAM
Machine cycle
Parameter System clock Ports D, E, G output
Pin name
Mi
Mi+1
STCK D0-D7,E0,E1 G0-G3 D0-D7 E0-E2 G0-G3
Ports D, E, G input
Rev.1.00 Aug 06, 2008 REJ03B0251-0100
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4286 Group
PACKAGE OUTLINE
JEITA Package Code P-LSSOP20-4.4x6.5-0.65 RENESAS Code PLSP0020JB-A Previous Code 20P2F-A MASS[Typ.] 0.1g
20
11
HE
*1
E
F
NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
1
Index mark
10
c
A2
A1
*2
D
Reference Symbol
Dimension in Millimeters
e y
*3
bp Detail F
D E A2 A A1 bp c HE e y L
Nom Max 6.5 6.6 4.4 4.5 1.15 1.45 0.1 0.2 0 0.17 0.22 0.32 0.13 0.15 0.2 0 10 6.2 6.4 6.6 0.53 0.65 0.77 0.10 0.3 0.5 0.7
Rev.1.00 Aug 06, 2008 REJ03B0251-0100
A
page 64 of 64
L
Min 6.4 4.3
REVISION HISTORY
Rev. Date Page
-
4286 Group Datasheet
Description Summary
1.00 Aug. 06, 2008
First edition issued.
All trademarks and registered trademarks are the property of their respective owners.
(1/1)
Sales Strategic Planning Div.
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When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. 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